supratimdas / NoobsCpu-8bitLinks
A simple 8bit CPU.
☆26Updated 6 months ago
Alternatives and similar repositories for NoobsCpu-8bit
Users that are interested in NoobsCpu-8bit are comparing it to the libraries listed below
Sorting:
- Introductory course into static timing analysis (STA).☆94Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆25Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- ☆41Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- BlackParrot on Zynq☆41Updated 3 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆74Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- A collection of commonly asked RTL design interview questions☆30Updated 8 years ago
- UVM and System Verilog Manuals☆42Updated 6 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆57Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆18Updated last week
- Implementation of RISC-V RV32I☆19Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆61Updated 4 years ago
- Static Timing Analysis Full Course☆56Updated 2 years ago