supratimdas / NoobsCpu-8bitLinks
A simple 8bit CPU.
☆26Updated 6 months ago
Alternatives and similar repositories for NoobsCpu-8bit
Users that are interested in NoobsCpu-8bit are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- Introductory course into static timing analysis (STA).☆95Updated 2 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Static Timing Analysis Full Course☆56Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- Structured UVM Course☆43Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆63Updated last year
- ☆41Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- System Verilog BootCamp☆24Updated 3 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆19Updated last month
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆57Updated 2 years ago
- Complete tutorial code.☆21Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆103Updated 4 years ago