supratimdas / NoobsCpu-8bit
A simple 8bit CPU.
☆25Updated 4 months ago
Alternatives and similar repositories for NoobsCpu-8bit:
Users that are interested in NoobsCpu-8bit are comparing it to the libraries listed below
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆62Updated last year
- ☆40Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- ☆12Updated last week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆73Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆29Updated last year
- BlackParrot on Zynq☆38Updated last month
- Two Level Cache Controller implementation in Verilog HDL☆42Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 3 weeks ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Complete tutorial code.☆17Updated 11 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆56Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- ☆89Updated last year
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆57Updated 4 years ago
- System Verilog BootCamp☆23Updated 3 years ago
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆63Updated 3 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago