supratimdas / NoobsCpu-8bitLinks
A simple 8bit CPU.
☆26Updated 8 months ago
Alternatives and similar repositories for NoobsCpu-8bit
Users that are interested in NoobsCpu-8bit are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆59Updated 2 years ago
- SystemVerilog Tutorial☆160Updated 3 months ago
- Introductory course into static timing analysis (STA).☆96Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- ☆97Updated last year
- RISC-V Verification Interface☆100Updated 2 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆56Updated 2 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆104Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- ☆41Updated 3 years ago
- Verilog/SystemVerilog Guide☆69Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆73Updated 4 years ago
- Structured UVM Course☆45Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 7 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆51Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 3 weeks ago
- Static Timing Analysis Full Course☆57Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 3 years ago
- Course content for the University of Bristol Design Verification course.☆58Updated 10 months ago
- This is a detailed SystemVerilog course☆113Updated 5 months ago