Repository to store all design and testbench files for Senior Design
☆22Apr 16, 2020Updated 6 years ago
Alternatives and similar repositories for senior_design_puf
Users that are interested in senior_design_puf are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA implementation of a physical unclonable function for authentication☆34Apr 7, 2017Updated 9 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆17Oct 10, 2020Updated 5 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Nov 24, 2017Updated 8 years ago
- Defense/Attack PUF Library (DA PUF Library)☆55May 5, 2020Updated 6 years ago
- Ring Oscillator Physically Unclonable Funtion☆25Sep 9, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆140Nov 5, 2022Updated 3 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- Hardware random number generator for FPGAs☆10May 7, 2015Updated 11 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- STM32 RFID Reader / Writer☆16May 24, 2014Updated 11 years ago
- ☆10Dec 26, 2023Updated 2 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Jun 29, 2022Updated 3 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆14Apr 1, 2020Updated 6 years ago
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆31Nov 8, 2025Updated 6 months ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- A fork of llama3.c used to do some R&D on inferencing☆22Dec 20, 2024Updated last year
- Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.☆13Dec 5, 2019Updated 6 years ago
- ☆23Jul 3, 2024Updated last year
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆28Mar 11, 2022Updated 4 years ago
- C++ library for AXI DMA with direct and scatter-gather support☆13Feb 22, 2022Updated 4 years ago
- Benchmarking execution time of AlexNet CNN on FPGA and GPU. Developed AlexNet in opencl.☆11Oct 9, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Nov 15, 2019Updated 6 years ago
- A tool to flash BL602 via JTAG + serial without pressing buttons / setting jumpers☆12Jun 3, 2022Updated 3 years ago
- ☆15Jul 14, 2024Updated last year
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆20Jan 21, 2022Updated 4 years ago
- The Subutai™ Router open hardware project sources.☆16Oct 2, 2017Updated 8 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Nov 26, 2024Updated last year
- Watch video on youtube☆18Nov 7, 2025Updated 6 months ago
- ☆17Jul 12, 2020Updated 5 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- GOST algorithms implementation for Linux Crypto subsystem☆14Jun 23, 2023Updated 2 years ago
- GOST R 34.12-2015 encryption algorithms implemented as loadable modules for Linux kernel☆13Jun 11, 2023Updated 2 years ago
- 100G Udp Link For axi Stream☆16Jun 27, 2023Updated 2 years ago
- Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm☆19Jan 4, 2026Updated 4 months ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 7 months ago
- ☆19Sep 15, 2022Updated 3 years ago
- ESP32 Wi-Fi, Ethernet, and 4G/LTE Network Router☆13Apr 12, 2023Updated 3 years ago