Crimsonninja / senior_design_pufLinks
Repository to store all design and testbench files for Senior Design
☆21Updated 5 years ago
Alternatives and similar repositories for senior_design_puf
Users that are interested in senior_design_puf are comparing it to the libraries listed below
Sorting:
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 8 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆11Updated 6 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 6 years ago
- ☆21Updated 2 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆16Updated 5 years ago
- Defense/Attack PUF Library (DA PUF Library)☆54Updated 5 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 8 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Updated 7 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Ring Oscillator Physically Unclonable Funtion☆26Updated 4 years ago
- few python scripts to clone all IP cores from opencores.org☆25Updated last year
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆38Updated 4 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- Side-channel analysis setup for OpenTitan☆37Updated last month
- ☆60Updated 4 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Updated 6 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 7 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Updated last month
- ☆25Updated last week
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago