Alternatives and similar repositories for RISC-V-5-stage-pipelined-in-verilog

Users that are interested in RISC-V-5-stage-pipelined-in-verilog are comparing it to the libraries listed below

• Devipriya1921 / VSDBabySoC_ICC2
  ☆10Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆49Updated 11 months ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆22Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 9 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆10Updated 9 months ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆33Updated 3 years ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆19Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆11Updated 11 months ago
• arunkpv / vsd-hdp
  ☆17Updated 3 weeks ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• Devipriya1921 / Traffic-Light-Controller-using-Verilog
  Verilog Project
  ☆11Updated 3 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆79Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆70Updated 5 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆62Updated last year
• maazm007 / vsdsquadron-mini-internship
  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
  ☆27Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆60Updated 2 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆71Updated 2 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆19Updated 2 years ago
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆27Updated 6 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆34Updated 4 years ago
• mvgprasanth / Systolic-Array-Matrix-Multiplication
  Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256
  ☆20Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆42Updated last year
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆9Updated 2 years ago