lesc-ufv / cad4u
Cad4u
☆12Updated 3 months ago
Alternatives and similar repositories for cad4u:
Users that are interested in cad4u are comparing it to the libraries listed below
- Learning how to make a RISC-V☆135Updated 3 years ago
- ☆10Updated 10 months ago
- ☆17Updated 2 weeks ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆22Updated 2 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆15Updated 4 months ago
- A tool for synthesizing Verilog programs☆63Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- Development of a complete environment to teach and learn computer architecture, VHDL processor design and Assembly language☆73Updated 8 months ago
- ☆40Updated last year
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆13Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆71Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆146Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆140Updated last year
- ☆109Updated last year
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- An overview of TL-Verilog resources and projects☆73Updated 11 months ago
- A scalable High-Level Synthesis framework on MLIR☆245Updated 9 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆43Updated 3 weeks ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆13Updated 2 years ago
- Tutorial de instalação do Quartus Prime no Linux☆37Updated 5 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆14Updated 3 months ago
- VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.☆25Updated 6 months ago
- SystemVerilog synthesis tool☆177Updated this week
- ☆132Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- Repositório de Análise de Dados e Data Science☆13Updated 2 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated 2 weeks ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆198Updated 3 months ago
- ☆309Updated last year
- ☆124Updated 7 months ago