Alternatives and similar repositories for cad4u

Users that are interested in cad4u are comparing it to the libraries listed below

• menotti / pp
  Curso de Programação Paralela
  ☆10Updated 2 years ago
• racerxdl / riskow
  Learning how to make a RISC-V
  ☆135Updated 4 years ago
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆428Updated 8 months ago
• andremarinho17 / data_projects
  Repositório de Análise de Dados e Data Science
  ☆13Updated 11 months ago
• JN513 / Risco-5
  Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
  ☆17Updated last year
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆112Updated 4 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆106Updated 2 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆122Updated last month
• arthurmteodoro / install-quartus-linux
  Tutorial de instalação do Quartus Prime no Linux
  ☆39Updated 6 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆179Updated last week
• laplaceyc / VLSI_Design-Implementation
  This repo is "NTHU VLSI System Design and Implementation" course project.
  ☆13Updated 8 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 7 months ago
• ncsu-eda / FreePDK3
  ☆181Updated 4 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆138Updated 5 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆81Updated 2 years ago
• chipsalliance / silicon-notebooks
  ☆173Updated 2 years ago
• hughbyrne10 / 100daysofRTL
  100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…
  ☆27Updated 2 years ago
• LSC-Unicamp / processor-ci-website
  Processor CI project Website
  ☆10Updated 4 months ago
• antonson-j1 / SHA256-Accelerator-Hardware
  This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU…
  ☆27Updated 3 years ago
• LucasBraganca / ModeloLatexTeseUFV
  ☆10Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆55Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆112Updated 2 years ago
• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆10Updated 10 months ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆186Updated 3 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 5 years ago
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆29Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆149Updated last week
• nickson-jose / openlane_build_script
  This script builds openlane and all its dependencies on an Ubuntu (only) System.
  ☆23Updated 3 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆219Updated this week