joycenerd / DNN-accelerator-on-zynq
Digital Design Lab Spring 2019 Final Project
☆11Updated 5 years ago
Alternatives and similar repositories for DNN-accelerator-on-zynq
Users that are interested in DNN-accelerator-on-zynq are comparing it to the libraries listed below
Sorting:
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆64Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆18Updated last month
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- AI Chip project☆31Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- IC implementation of TPU☆124Updated 5 years ago
- ☆70Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Open-source of MSD framework☆16Updated last year