joycenerd / DNN-accelerator-on-zynqLinks
Digital Design Lab Spring 2019 Final Project
☆12Updated 6 years ago
Alternatives and similar repositories for DNN-accelerator-on-zynq
Users that are interested in DNN-accelerator-on-zynq are comparing it to the libraries listed below
Sorting:
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆65Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- ☆71Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- AI Chip project☆31Updated 4 years ago
- ☆34Updated 6 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆25Updated 3 months ago
- IC implementation of TPU☆128Updated 5 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated 11 months ago
- ☆34Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago