joycenerd / DNN-accelerator-on-zynq
Digital Design Lab Spring 2019 Final Project
☆11Updated 5 years ago
Alternatives and similar repositories for DNN-accelerator-on-zynq:
Users that are interested in DNN-accelerator-on-zynq are comparing it to the libraries listed below
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- ☆69Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆48Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆36Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆15Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 5 months ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆60Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- 2020 xilinx summer school☆17Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Verilog implementation of Softmax function☆56Updated 2 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- ☆29Updated 5 years ago
- ☆56Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆13Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆13Updated 7 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆28Updated last year