ChrisPVille / mig_example
Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
☆31Updated 2 years ago
Alternatives and similar repositories for mig_example
Users that are interested in mig_example are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- Two Level Cache Controller implementation in Verilog HDL☆45Updated 4 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Simple cache design implementation in verilog☆46Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- ☆24Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆68Updated 4 years ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 3 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- ☆19Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Altera Advanced Synthesis Cookbook 11.0☆103Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year