ChrisPVille / mig_exampleLinks
Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
☆34Updated 3 years ago
Alternatives and similar repositories for mig_example
Users that are interested in mig_example are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 2 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆55Updated 5 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆59Updated 6 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- A Verilog implementation of a processor cache.☆31Updated 7 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆34Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆89Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆117Updated last year
- RISC V core implementation using Verilog.☆27Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆126Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆44Updated 8 years ago
- Verilog digital signal processing components☆159Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆51Updated last year
- Simple cache design implementation in verilog☆53Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- AHB3-Lite Interconnect☆95Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 10 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- Simple single-port AXI memory interface☆47Updated last year
- Interface Protocol in Verilog☆50Updated 6 years ago