ChrisPVille / mig_exampleLinks
Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
☆31Updated 3 years ago
Alternatives and similar repositories for mig_example
Users that are interested in mig_example are comparing it to the libraries listed below
Sorting:
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- Altera Advanced Synthesis Cookbook 11.0☆104Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- ☆41Updated last year
- A Verilog implementation of a processor cache.☆26Updated 7 years ago
- ☆25Updated last year
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Simple single-port AXI memory interface☆41Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆41Updated 3 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆72Updated 2 years ago
- ☆12Updated 2 months ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- round robin arbiter☆74Updated 10 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆17Updated 2 years ago
- 2D Systolic Array Multiplier☆16Updated last year
- Static Timing Analysis Full Course☆56Updated 2 years ago
- ☆34Updated 6 years ago