ashleyjr / Verilog
☆10Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for Verilog
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆57Updated 5 months ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- ☆11Updated last year
- ideas and eda software for vlsi design☆47Updated this week
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago
- APB UVC ported to Verilator☆11Updated last year
- ☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Automatic generation of real number models from analog circuits☆37Updated 7 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Running Python code in SystemVerilog☆63Updated 4 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆30Updated last year
- ☆39Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 3 weeks ago
- slang-based frontend for Yosys☆43Updated this week
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- ☆9Updated last year
- LibreSilicon's Standard Cell Library Generator☆17Updated 6 months ago
- Making cocotb testbenches that bit easier☆24Updated last week
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆30Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆43Updated last year
- Open FPGA Modules☆23Updated last month
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆26Updated last month
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago