Alternatives and similar repositories for single_cycle_RISCV_CPU_Design-32bit

Users that are interested in single_cycle_RISCV_CPU_Design-32bit are comparing it to the libraries listed below

• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆146Updated last year
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆161Updated 7 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆105Updated last year
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆69Updated last year
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆34Updated 4 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆33Updated 3 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆96Updated 3 weeks ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆14Updated 4 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆136Updated 2 years ago
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆134Updated 5 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆193Updated last year
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆18Updated 4 years ago
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆35Updated last year
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• redlightASl / Notes
  ☆86Updated last month
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆127Updated last year
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• OSCPU / ysyx-workbench
  ☆160Updated last month
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• Jasonyanyusong / ysyx-npc-workbench
  一生一芯RISCV处理器核代码仓库（包括相关工具）
  ☆15Updated last year
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆54Updated 3 years ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆32Updated last year
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆182Updated 4 years ago
• SinnLiu / CPU_Design_MIPS
  《CPU设计实战》学习记录及代码
  ☆13Updated 2 years ago