Alternatives and similar repositories for single_cycle_RISCV_CPU_Design-32bit:

Users that are interested in single_cycle_RISCV_CPU_Design-32bit are comparing it to the libraries listed below

• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆77Updated 5 years ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆12Updated 3 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆28Updated 3 years ago
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆131Updated 10 months ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆62Updated 8 months ago
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆23Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆54Updated 3 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• OSCPU / yosys-sta
  ☆63Updated this week
• wzp21142 / mips-cpu-and-microsystem
  基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instructi…
  ☆18Updated 4 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆145Updated 6 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆90Updated 2 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆23Updated 10 months ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆51Updated last year
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆27Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆64Updated 2 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆23Updated last year
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 5 years ago
• CherrySprings / CherrySprings
  ☆18Updated last year
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆55Updated 4 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆71Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆130Updated last year
• OSCPU / ysyx-exam
  ☆21Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 11 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆129Updated 5 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆105Updated 10 months ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago