Alternatives and similar repositories for Floating-Point-Adder

Users that are interested in Floating-Point-Adder are comparing it to the libraries listed below

• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆44Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆112Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 7 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆97Updated 6 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆78Updated 3 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆33Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆78Updated 7 years ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆37Updated last year
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆62Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆60Updated 2 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆198Updated 3 months ago
• mcjtag / bitonic_sorter
  Bitonic sorter (Batcher's sorting network) written in Verilog.
  ☆35Updated last year
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆13Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆140Updated 7 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆76Updated last month
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆66Updated 3 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆22Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆50Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆74Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆99Updated 6 years ago