32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog
☆18Aug 27, 2020Updated 5 years ago
Alternatives and similar repositories for Floating-Point-Adder
Users that are interested in Floating-Point-Adder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of 32-bit Floating Point Adder☆49May 4, 2020Updated 6 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆70Aug 10, 2024Updated last year
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 3 months ago
- Awesome Quantization Paper lists with Codes☆10Feb 24, 2021Updated 5 years ago
- Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102☆19May 30, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Aug 26, 2021Updated 4 years ago
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated last year
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆30Mar 13, 2025Updated last year
- Use Matlab to simulate in LT Spice, acquire results and plot☆18Oct 22, 2020Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆123Jan 26, 2013Updated 13 years ago
- Implementing Different Adder Structures in Verilog☆75Sep 3, 2019Updated 6 years ago
- ☆12Jun 9, 2022Updated 4 years ago
- ☆10Jun 28, 2019Updated 6 years ago
- ☆23Feb 22, 2020Updated 6 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- Deep Variational Information Bottleneck (DVIB) in PyTorch.☆10Apr 25, 2020Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆41Apr 28, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Qimera: Data-free Quantization with Synthetic Boundary Supporting Samples [NeurIPS 2021]☆34Dec 12, 2021Updated 4 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 5 years ago
- ☆17Apr 23, 2018Updated 8 years ago
- This script generates and analyzes prefix tree adders.☆38Apr 9, 2021Updated 5 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 6 months ago
- TensorRT-in-Action 是一个 GitHub 代码库，提供了使用 TensorRT 的代码示例，并有对应 Jupyter Notebook。☆15Jun 1, 2023Updated 3 years ago
- Low Precision Arithmetic Simulation in PyTorch - extension for posit and beyond☆16Dec 9, 2025Updated 6 months ago
- Open Component Portability Infrastructure☆62May 1, 2021Updated 5 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆14Mar 21, 2020Updated 6 years ago
- Booth encoded Wallace tree multiplier☆17May 24, 2018Updated 8 years ago
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Nov 8, 2021Updated 4 years ago
- TLLM_QMM strips the implementation of quantized kernels of Nvidia's TensorRT-LLM, removing NVInfer dependency and exposes ease of use Pyt…☆16Jul 5, 2024Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- 32-bit soft RISCV processor for FPGA applications☆19Nov 25, 2023Updated 2 years ago
- ☆46May 8, 2020Updated 6 years ago