ArchC / ArchCLinks
A powerful and modern open-source architecture description language.
☆47Updated 8 years ago
Alternatives and similar repositories for ArchC
Users that are interested in ArchC are comparing it to the libraries listed below
Sorting:
- Documentation for the BOOM processor☆47Updated 8 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last week
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A Tiny Processor Core☆114Updated 6 months ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- A reconfigurable and extensible VLIW processor implemented in VHDL☆39Updated 10 years ago
- Visual Simulation of Register Transfer Logic☆109Updated 4 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- ☆61Updated 4 years ago
- ☆147Updated last year
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- This is the Verilog 2005 parser used by VerilogCreator☆15Updated 6 years ago
- The specification for the FIRRTL language☆62Updated last week
- Testing processors with Random Instruction Generation☆50Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- ☆51Updated last week
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 9 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆32Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago