zyedidia / riscinator
A tiny 3-stage RISC-V core written in Chisel.
☆13Updated last year
Alternatives and similar repositories for riscinator:
Users that are interested in riscinator are comparing it to the libraries listed below
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 3 weeks ago
- RISC-V Dynamic Debugging Tool☆46Updated last year
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆15Updated 5 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆32Updated last week
- Custom 64-bit pipelined RISC processor☆17Updated 8 months ago
- OpenRISC processor IP core based on Tomasulo algorithm☆10Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- riscv-linux musl gcc toolchain bootstrap scripts☆17Updated 4 years ago
- Peephole optimizer for cproc and QBE☆25Updated 2 years ago
- A bit-serial CPU☆18Updated 5 years ago
- A compiler for the Micron programming language - the Oberon with the power of C☆25Updated this week
- Minimal LISP Compiler for x86_64☆10Updated 3 years ago
- ☆23Updated 8 months ago
- Sparc emulator☆10Updated 6 years ago
- LolaCreator is a QtCreator based IDE for Lola-2☆15Updated 2 years ago
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago
- Parametric GPIO Peripheral☆11Updated 2 months ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆10Updated last year
- RISC-V Configuration Structure☆37Updated 5 months ago
- RISC-V BSV Specification☆20Updated 5 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆17Updated 3 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- ☆13Updated this week
- A Basic C++ RISC-V Emulator☆17Updated 4 years ago
- Gatery, a library for circuit design.☆19Updated 3 months ago
- Minimal microprocessor☆20Updated 7 years ago
- This implementation of file system is developed by ELM Chan☆14Updated last month
- Memory Simulator and Optimizer☆23Updated 5 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆19Updated last month
- RTL blocks compatible with the Rocket Chip Generator☆14Updated this week