zyedidia / riscinator
A tiny 3-stage RISC-V core written in Chisel.
☆13Updated last year
Alternatives and similar repositories for riscinator:
Users that are interested in riscinator are comparing it to the libraries listed below
- OpenRISC processor IP core based on Tomasulo algorithm☆10Updated 2 years ago
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆29Updated this week
- A bit-serial CPU☆18Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last week
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- An Open Source Link Protocol and Controller☆24Updated 3 years ago
- riscv-linux musl gcc toolchain bootstrap scripts☆17Updated 3 years ago
- RISC-V Dynamic Debugging Tool☆46Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A design for TinyTapeout☆15Updated 2 years ago
- A powerful and modern open-source architecture description language.☆41Updated 7 years ago
- Custom 64-bit pipelined RISC processor☆16Updated 6 months ago
- RISC-V Configuration Structure☆37Updated 3 months ago
- Minimal microprocessor☆20Updated 7 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Memory Simulator and Optimizer☆23Updated 5 years ago
- The SiFive wake build tool☆87Updated last week
- squint - Rob Pike's Newsqueak interpreter for Unix☆36Updated 12 years ago
- Standalone C compiler for RISC-V and ARM☆78Updated 8 months ago
- RISC-V BSV Specification☆18Updated 5 years ago
- A Basic C++ RISC-V Emulator☆17Updated 4 years ago
- Source-Opened RISCV for Crypto☆15Updated 3 years ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 7 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆36Updated 9 months ago
- a Plan 9-like system based using tamago☆16Updated last year
- A very simple RISC-V ISA emulator.☆37Updated 4 years ago
- RISC-V 32-bit Linux From Scratch☆32Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆44Updated last month