Alternatives and similar repositories for ac_types

Users that are interested in ac_types are comparing it to the libraries listed below

• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆125Updated last year
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆165Updated last week
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆284Updated 2 weeks ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆65Updated 5 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆226Updated last week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆148Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆269Updated last month
• rdaly525 / coreir
  ☆104Updated 3 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆115Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆180Updated last year
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆110Updated 5 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last month
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆225Updated 3 weeks ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆288Updated 2 weeks ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆121Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆179Updated 10 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆397Updated 3 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 5 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆115Updated 3 weeks ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆115Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week