Algorithmic C Datatypes
☆140Sep 10, 2026Updated last month
Alternatives and similar repositories for ac_types
Users that are interested in ac_types are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Algorithmic C Math Library☆68Updated this week
- Algorithmic C Digital Signal Processing (DSP) Library☆54Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆303Sep 2, 2026Updated last month
- Tutorials on HLS Design☆51Jan 16, 2020Updated 6 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated this week
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- SYCL-based 2D Stencil Simulation Framework☆19May 3, 2026Updated 5 months ago
- SoCRocket - Core Repository☆40Mar 6, 2017Updated 9 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆320Sep 25, 2026Updated 3 weeks ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆26Oct 6, 2026Updated last week
- A header only C++11 library for functional coverage☆35Oct 7, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- XLS: Accelerated HW Synthesis☆1,953Updated this week
- Xilinx Unisim Library in Verilog☆93Jul 22, 2020Updated 6 years ago
- RISC-V SystemC-TLM simulator☆361Feb 20, 2026Updated 7 months ago
- Constrained random stimuli generation for C++ and SystemC☆54Nov 29, 2023Updated 2 years ago
- Unified Coverage Interoperability Standard (UCIS)☆15Sep 2, 2026Updated last month
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- ☆13Aug 22, 2022Updated 4 years ago
- ☆226Aug 16, 2026Updated 2 months ago
- Basic Common Modules☆48Oct 5, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Python packages providing a library for Verification Stimulus and Coverage☆149Updated this week
- OpenFPGA☆34Mar 12, 2018Updated 8 years ago
- Example FPGA programs written using LegUp HLS☆11May 13, 2021Updated 5 years ago
- IP-XACT XML binding library☆17Jun 23, 2016Updated 10 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 5 years ago
- RISC-V GPGPU☆40Mar 6, 2020Updated 6 years ago
- FPGA and Digital ASIC Build System☆87Updated this week
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- ☆19Jan 29, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Intel Compiler for SystemC☆31Jun 1, 2023Updated 3 years ago
- ☆13Jul 24, 2026Updated 2 months ago
- Algorithmic C Machine Learning Library☆29Updated this week
- Interconnect Prototyping Assistant (IPA) is an interconnect modeling and generation framework built atop [MatchLib] (https://github.com/N…☆15Aug 20, 2024Updated 2 years ago
- A simple C++ CMake project to jump-start development of SystemC models and systems☆31Nov 24, 2024Updated last year
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year