Algorithmic C Datatypes
☆135Jan 6, 2026Updated last month
Alternatives and similar repositories for ac_types
Users that are interested in ac_types are comparing it to the libraries listed below
Sorting:
- Algorithmic C Math Library☆67Jan 6, 2026Updated last month
- Algorithmic C Digital Signal Processing (DSP) Library☆52Jan 6, 2026Updated last month
- Tutorials on HLS Design☆51Jan 16, 2020Updated 6 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆293Oct 30, 2025Updated 4 months ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated last year
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- Intel Compiler for SystemC☆29Jun 1, 2023Updated 2 years ago
- SoCRocket - Core Repository☆38Mar 6, 2017Updated 8 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- RISC-V SystemC-TLM simulator☆340Feb 20, 2026Updated last week
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆140Feb 18, 2026Updated 2 weeks ago
- A low-level intermediate representation for hardware description languages☆28Jun 28, 2020Updated 5 years ago
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Jul 22, 2020Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Jan 6, 2026Updated last month
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- XLS: Accelerated HW Synthesis☆1,428Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Feb 26, 2026Updated last week