Alternatives and similar repositories for mlpolygen

Users that are interested in mlpolygen are comparing it to the libraries listed below

• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆199Updated 2 months ago
• olofk / corescore
  CoreScore
  ☆162Updated 2 weeks ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆180Updated 2 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆112Updated this week
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 2 years ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆174Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 4 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 8 months ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated 4 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆95Updated 3 years ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆134Updated 2 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated last week
• TinyTapeout / tinytapeout_gds_viewer
  Tiny Tapeout GDS Online Viewer
  ☆19Updated last week
• mnemocron / my-discrete-fpga
  My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
  ☆43Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆87Updated last month
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆93Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 4 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆107Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆86Updated 3 weeks ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆53Updated this week
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆62Updated 3 months ago
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆39Updated last year