f4pga / prjtrellis
Documenting the Lattice ECP5 bit-stream format.
☆53Updated last year
Alternatives and similar repositories for prjtrellis:
Users that are interested in prjtrellis are comparing it to the libraries listed below
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆72Updated 2 years ago
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- A padring generator for ASICs☆24Updated last year
- Experimental flows using nextpnr for Xilinx devices☆41Updated last month
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆83Updated 6 years ago
- nextpnr portable FPGA place and route tool☆20Updated 4 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated this week
- PicoRV☆44Updated 4 years ago
- A wishbone controlled scope for FPGA's☆74Updated last year
- Nitro USB FPGA core☆84Updated 10 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- A pipelined RISC-V processor☆48Updated last year
- Example LED blinking project for your FPGA dev board of choice☆168Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆33Updated 4 years ago
- Xilinx Unisim Library in Verilog☆72Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 2 years ago
- FuseSoC standard core library☆124Updated 3 weeks ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆93Updated 5 months ago
- Naive Educational RISC V processor☆77Updated 3 months ago
- ☆39Updated 3 weeks ago
- Tiny tips for Colorlight i5 FPGA board☆56Updated 3 years ago
- ☆40Updated 10 months ago
- A basic Soft(Gate)ware Defined Radio architecture☆76Updated last year
- This repository contains small example designs that can be used with the open source icestorm flow.☆143Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆77Updated 4 months ago
- Drawio => VHDL and Verilog☆51Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆64Updated 6 months ago