Alternatives and similar repositories for neoTRNG:

Users that are interested in neoTRNG are comparing it to the libraries listed below

• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆131Updated 2 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆175Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆178Updated 3 weeks ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆410Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆234Updated 6 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆324Updated 2 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆177Updated this week
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆236Updated 2 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆282Updated this week
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆135Updated last month
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆135Updated 2 years ago
• mattvenn / awesome-opensource-asic-resources
  ☆321Updated 2 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆167Updated last year
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆282Updated 2 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆178Updated 4 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆334Updated 2 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆145Updated 10 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆264Updated 2 months ago
• olofk / corescore
  CoreScore
  ☆151Updated 3 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆163Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last week
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆319Updated 2 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆250Updated 2 weeks ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆427Updated 7 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆136Updated last week