Alternatives and similar repositories for neoTRNG

Users that are interested in neoTRNG are comparing it to the libraries listed below

• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆136Updated 3 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆248Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated last week
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆259Updated 3 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆460Updated 2 weeks ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆186Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• olofk / corescore
  CoreScore
  ☆170Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆353Updated last month
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆84Updated last month
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆188Updated 2 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆182Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆298Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆415Updated 11 months ago
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆160Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆244Updated 2 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆364Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated 2 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆158Updated last year
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆271Updated last month
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆281Updated last year
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆139Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆169Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 9 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year