π² A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
β220May 7, 2026Updated this week
Alternatives and similar repositories for neoTRNG
Users that are interested in neoTRNG are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.β140Nov 5, 2022Updated 3 years ago
- True Random Number Generator core implemented in Verilog.β84Oct 8, 2020Updated 5 years ago
- π₯οΈ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independeβ¦β2,055Updated this week
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.β13Nov 26, 2024Updated last year
- π Add capacitive touch buttons to any FPGA!β104Mar 4, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean β’ AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- β10Apr 8, 2021Updated 5 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware accelerationβ47Nov 24, 2025Updated 5 months ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.β12Sep 22, 2020Updated 5 years ago
- VHDLproc is a VHDL preprocessorβ24May 12, 2022Updated 3 years ago
- Library of reusable VHDL componentsβ28Mar 7, 2024Updated 2 years ago
- Experiments with Cologne Chip's GateMate FPGA architectureβ18Nov 16, 2023Updated 2 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.β17Mar 26, 2026Updated last month
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formatsβ51Apr 8, 2023Updated 3 years ago
- general-coresβ21Jul 16, 2025Updated 9 months ago
- End-to-end encrypted email - Proton Mail β’ AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Generate symbols from HDL components/modulesβ22Feb 6, 2023Updated 3 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFsβ14Apr 1, 2020Updated 6 years ago
- SERV - The SErial RISC-V CPUβ1,793Feb 19, 2026Updated 2 months ago
- Multi-platform nightly builds of open source FPGA toolsβ302Nov 3, 2021Updated 4 years ago
- A huge VHDL library for FPGA and digital ASIC developmentβ457Updated this week
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLMβ16Mar 25, 2025Updated last year
- Baseband Receiver IP for GPS like DSSS signalsβ41May 19, 2020Updated 5 years ago
- Benchmark suite for real-time behavior, including interrupt latency and context switching timesβ15Oct 20, 2021Updated 4 years ago
- RISCV CPU implementation in SystemVerilogβ32Mar 17, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient β’ AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Examples and design pattern for VHDL verificationβ15Apr 10, 2016Updated 10 years ago
- π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.β33Aug 20, 2022Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 featuresβ32Jan 30, 2025Updated last year
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and piβ¦β1,412Apr 28, 2026Updated last week
- An all-digital GPS disciplined oscillator using MMCM phase shift.β32Sep 1, 2022Updated 3 years ago
- VHDL Implementation of AES Algorithmβ92Jul 29, 2021Updated 4 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.β75Feb 18, 2026Updated 2 months ago
- Small footprint and configurable Inter-Chip communication coresβ66Feb 20, 2026Updated 2 months ago
- A bit-serial CPUβ20Sep 29, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- IEEE 754 single precision floating point library in systemverilog and vhdlβ41Apr 28, 2026Updated last week
- RISC-V Nox coreβ73Jul 22, 2025Updated 9 months ago
- Basic Pong you can extend with rotary, sound, vga generator and autopilotβ11Oct 26, 2021Updated 4 years ago
- VHDL compiler and simulatorβ810Updated this week
- Repository containing the DSP gateware coresβ14Mar 9, 2026Updated 2 months ago
- An abstract language model of VHDL written in Python.β64Updated this week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designsβ189Mar 10, 2024Updated 2 years ago