buxiangqimingle233 / pynq_based_cnn_acceleratorLinks
cnn accelerator in vivado HLS
☆9Updated 3 years ago
Alternatives and similar repositories for pynq_based_cnn_accelerator
Users that are interested in pynq_based_cnn_accelerator are comparing it to the libraries listed below
Sorting:
- 2020 xilinx summer school☆17Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆9Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- ☆26Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- The CNN based on the Xilinx Vivado HLS☆36Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Updated 4 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆23Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- ☆27Updated 2 months ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- ☆10Updated 6 months ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 4 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago