cea-wind / hls_ldpc_decLinks
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
☆37Updated 6 years ago
Alternatives and similar repositories for hls_ldpc_dec
Users that are interested in hls_ldpc_dec are comparing it to the libraries listed below
Sorting:
- NMS_decode☆13Updated 4 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆67Updated 2 years ago
- Polar Codes Implementation on Vhdl☆13Updated 9 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆50Updated 7 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆46Updated 6 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆104Updated 11 months ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- IEEE 802.11 OFDM-based transceiver system☆34Updated 7 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆35Updated 7 months ago
- The source codes of the fast x86 LDPC decoder published☆26Updated 4 years ago
- 最小和算法实现☆10Updated 4 years ago
- Playing with Low-density parity-check codes☆94Updated 2 years ago
- Verilog实现OFDM基带☆43Updated 9 years ago
- A matlab implementation of the 802.11n LDPC encoder and decoder☆62Updated 3 years ago
- ☆12Updated 3 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆22Updated 4 years ago
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- Playground for implementing LDPC codes on FPGA☆16Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆57Updated 6 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆17Updated 3 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆13Updated this week
- Low Density Parity Check codes encoder and decoder, in particular for CCSDS standards.☆62Updated 6 years ago
- Low Density Parity Check Decoder☆15Updated 8 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆49Updated 2 years ago
- Matlab simulations of the encoder and decoder for the New Radio LDPC code from 3GPP Release 15☆49Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Updated 4 years ago
- construction high perfomance long length, low error floor block Multi-edge Type (MET) QC-LDPC codes and Tail-Biting convolutional MET QC-…☆29Updated last year
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆15Updated 6 years ago
- ☆28Updated last year