lisliyongming / JESD204BLinks
通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
☆23Updated 5 years ago
Alternatives and similar repositories for JESD204B
Users that are interested in JESD204B are comparing it to the libraries listed below
Sorting:
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆17Updated 7 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- ☆31Updated 5 years ago
- FPGA Technology Exchange Group相关文件管理☆45Updated last month
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆66Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆77Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- verilog☆21Updated last year
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆57Updated 6 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 4 years ago
- FPGA implementation of pose detection with Kalman filter. (verilog)☆35Updated 3 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆49Updated 2 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆46Updated 3 years ago
- 8b10b Encoder/Decoder☆11Updated 10 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆59Updated 3 years ago
- Verilog实现OFDM基带☆43Updated 9 years ago
- An AXI DDR3 SDRAM controller for FPGA☆36Updated last year
- 基于FPGA的FFT☆17Updated 6 years ago
- AD7606 driver verilog☆41Updated 6 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- Hardware Viterbi Decoder in verilog☆26Updated 6 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21Updated 2 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆72Updated last year