lisliyongming / JESD204BLinks
通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
☆23Updated 6 years ago
Alternatives and similar repositories for JESD204B
Users that are interested in JESD204B are comparing it to the libraries listed below
Sorting:
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆61Updated 6 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆78Updated 2 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆60Updated 3 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆32Updated 4 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆53Updated 8 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆18Updated 8 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆62Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- Verilog实现OFDM基带☆44Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆72Updated last month
- Dual-Mode PSK Transceiver on SDR With FPGA☆49Updated last year
- IEEE 802.11 OFDM-based transceiver system☆41Updated 8 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆127Updated last month
- Hardware Assisted IEEE 1588 IP Core☆30Updated 11 years ago
- FPGA Technology Exchange Group相关文件管理☆54Updated last month
- Hardware Viterbi Decoder in verilog☆28Updated 6 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆57Updated 2 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆54Updated 4 years ago
- Verilog based BCH encoder/decoder☆130Updated 3 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆99Updated last year
- verilog☆21Updated 2 years ago
- ☆80Updated 3 years ago
- An AXI DDR3 SDRAM controller for FPGA☆42Updated last year
- Low Density Parity Check Decoder☆18Updated 9 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆77Updated 4 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- ☆32Updated 6 years ago