Alternatives and similar repositories for Design-and-Verification-of-LDPC-Decoder

Users that are interested in Design-and-Verification-of-LDPC-Decoder are comparing it to the libraries listed below

• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆76Updated 2 years ago
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆18Updated 5 years ago
• Hyacinth2333 / QC_LDPC-ECC
  NMS_decode
  ☆15Updated 5 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆22Updated 5 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• Spartak0s / Polar-Codes-Hardware-VHDL
  Polar Codes Implementation on Vhdl
  ☆13Updated 9 years ago
• crboth / LDPC_Decoder
  Low Density Parity Check Decoder
  ☆17Updated 9 years ago
• freedomhust / LDPC_MS
  最小和算法实现
  ☆10Updated 5 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆125Updated 3 years ago
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆28Updated 11 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆56Updated last year
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆65Updated 3 years ago
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆26Updated 6 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆121Updated last year
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• Mshivam2409 / LDPC-Decoder
  Implementation of Partially Parellel LDPC Code Decoder in Verilog
  ☆15Updated 5 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆29Updated 11 years ago
• arun1993 / FPGA-Wireless-communication-blocks
  Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS
  ☆27Updated 4 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆58Updated 6 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆60Updated 3 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆37Updated 4 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆79Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆67Updated last year
• ziruizhu / ofdm
  Toy OFDM Communication System with FPGA
  ☆12Updated 3 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆32Updated 2 years ago
• wangyuxiao2000 / ccsds-ldpc
  ccsds ldpc encdoer and decoder.(CCSDS 131.1-O-2)
  ☆24Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆22Updated 3 years ago