dshekhalev / FEC
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
☆99Updated 9 months ago
Alternatives and similar repositories for FEC:
Users that are interested in FEC are comparing it to the libraries listed below
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆63Updated last year
- Polar Codes Implementation on Vhdl☆12Updated 8 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆49Updated 7 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆52Updated last year
- 最小和算法实现☆10Updated 4 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆56Updated 5 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆172Updated last year
- PYNQ example of using the RFSoC as a QPSK transceiver.☆100Updated last year
- Verilog based BCH encoder/decoder☆119Updated 2 years ago
- IEEE 802.11 OFDM-based transceiver system☆33Updated 7 years ago
- NMS_decode☆13Updated 4 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆30Updated 6 months ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆46Updated last year
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆206Updated last year
- RTL implementation of components for DVB-S2☆116Updated last year
- An RFSoC Frequency Planner developed using Python.☆25Updated last year
- ☆11Updated 3 years ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆18Updated 4 months ago
- Hardware Assisted IEEE 1588 IP Core☆28Updated 10 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆37Updated 5 years ago
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆45Updated 6 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- A collection of phase locked loop (PLL) related projects☆104Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆35Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆49Updated 3 years ago
- Hardware Viterbi Decoder in verilog☆25Updated 5 years ago
- 10G Low Latency Ethernet☆50Updated last year
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆24Updated 5 years ago