Alternatives and similar repositories for FEC

Users that are interested in FEC are comparing it to the libraries listed below

• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆76Updated 2 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆105Updated 2 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆54Updated last year
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆50Updated 2 years ago
• Spartak0s / Polar-Codes-Hardware-VHDL
  Polar Codes Implementation on Vhdl
  ☆13Updated 9 years ago
• biren15 / Design-and-Verification-of-LDPC-Decoder
  - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …
  ☆52Updated 7 years ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆59Updated 6 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆121Updated 2 years ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆35Updated 7 years ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆40Updated 10 months ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆123Updated 2 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆79Updated 2 months ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆84Updated last year
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆26Updated 6 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• strath-sdr / RFSoC-Book
  Companion Jupyter Notebooks for the RFSoC-Book.
  ☆221Updated 2 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆30Updated 2 years ago
• catkira / open5G_phy
  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
  ☆210Updated 3 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆108Updated last year
• open-sdr / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆119Updated last month
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆23Updated 9 months ago
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆27Updated 11 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆23Updated 5 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆88Updated 2 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆31Updated 11 years ago
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆44Updated 9 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆150Updated 2 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆59Updated 2 years ago
• mathworks / HDL-Coder-Self-Guided-Tutorial
  Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.
  ☆83Updated 7 months ago