Grootzz / AD9361_TX_MSK
A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
☆54Updated 5 years ago
Alternatives and similar repositories for AD9361_TX_MSK:
Users that are interested in AD9361_TX_MSK are comparing it to the libraries listed below
- IEEE 802.11 OFDM-based transceiver system☆31Updated 7 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆26Updated 4 months ago
- Verilog实现OFDM基带☆42Updated 9 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆14Updated 6 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆45Updated last year
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆59Updated last year
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆25Updated 3 years ago
- NMS_decode☆12Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆51Updated 11 months ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆93Updated 7 months ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆123Updated last year
- ☆13Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆31Updated 3 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆50Updated 7 years ago
- 最小和算法实现☆11Updated 4 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆19Updated last year
- MATLAB-based FIR filter design☆52Updated 5 months ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆21Updated 4 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆17Updated 7 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆37Updated 5 years ago
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆97Updated last year
- Hardware Viterbi Decoder in verilog☆24Updated 5 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆42Updated 3 years ago
- ☆12Updated 7 years ago
- Using Software Designed Radio to transmit & receive FM signal☆43Updated 6 years ago
- MATLAB toolbox for ADI transceiver products☆59Updated 2 months ago