Alternatives and similar repositories for AD9361_TX_MSK

Users that are interested in AD9361_TX_MSK are comparing it to the libraries listed below

• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆51Updated last year
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆59Updated 2 weeks ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆42Updated 8 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆24Updated 6 years ago
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆45Updated 10 years ago
• lauchinyuan / FPGA_QPSK-modem
  A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
  ☆203Updated 2 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆129Updated last month
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆80Updated 2 years ago
• adimitris / verilog-LDPC-decoder
  A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)
  ☆11Updated 5 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆110Updated this week
• open-sdr / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆130Updated last month
• Grootzz / AD9361_TX_GMSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK
  ☆16Updated 7 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆33Updated 4 years ago
• MicroPhase / antsdr_standalone
  Standalone application based on ADI hdl and no_OS for ANTSDR.
  ☆23Updated 10 months ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆58Updated 4 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆59Updated last year
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆130Updated 2 years ago
• analogdevicesinc / ad936x-filter-wizard
  MATLAB-based FIR filter design
  ☆62Updated last year
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆61Updated 3 years ago
• FlyHighInSky / OFDM-on-FPGA
  ☆18Updated 3 years ago
• biren15 / Design-and-Verification-of-LDPC-Decoder
  - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …
  ☆54Updated 8 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• MazinLab / RFSoC_OPFB
  A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC
  ☆41Updated last year
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆29Updated 11 years ago
• lzk2211 / Zedboard_AD9361_radar
  We made ISAC radar using Zedboard and AD9361, by receiving the transmitted chirp signals, calculating the autocorrelation and FFT to get …
  ☆17Updated last year
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆87Updated 2 months ago
• Elrori / FMCW_Radar
  FMCW Radar verilog project
  ☆32Updated 5 years ago
• Hyacinth2333 / QC_LDPC-ECC
  NMS_decode
  ☆14Updated 5 years ago
• phthinh / OFDM_802_16
  IEEE 802.16 OFDM-based transceiver system
  ☆28Updated 6 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆64Updated 2 weeks ago