Alternatives and similar repositories for fluent10g

Users that are interested in fluent10g are comparing it to the libraries listed below

• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆68Updated 8 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆106Updated 7 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆61Updated this week
• maltevesper / JetStream-hardware
  ☆21Updated 9 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆34Updated 9 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 9 months ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆121Updated this week
• UofT-HPRC / fpga-bpf
  A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
  ☆49Updated 4 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆48Updated 2 years ago
• datenlord / blue-udp
  The hardware implementation of UDP in Bluespec SystemVerilog
  ☆12Updated last year
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 5 months ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆70Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆24Updated 2 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated 2 months ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last week