aoeldemann / fluent10g

Related projects: ⓘ

• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆53Updated 4 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆30Updated last year
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆60Updated 7 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆39Updated 3 years ago
• UofT-HPRC / fpga-bpf
  A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
  ☆43Updated 3 years ago
• aomtoku / hdmi-ts
  hdmi-ts Project
  ☆13Updated 7 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 2 months ago
• grebe / ofdm
  Chisel Things for OFDM
  ☆30Updated 4 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆23Updated 6 years ago
• corundum / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆14Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated 3 weeks ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 5 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆33Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆28Updated this week
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆22Updated last week
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆23Updated 5 years ago
• FDU-ME-ARC / NVMeCHA
  ☆12Updated 3 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• esnet / esnet-fpga-library
  ESnet general-purpose FPGA design library.
  ☆10Updated this week
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆31Updated 8 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆24Updated 3 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆28Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆49Updated last year
• subutai-attic / pars
  ☆28Updated 7 years ago