A FPGA implementation of the NTP and NTS protocols
☆70May 31, 2023Updated 3 years ago
Alternatives and similar repositories for FPGA_NTP_SERVER
Users that are interested in FPGA_NTP_SERVER are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- High-Speed Stateful Packet Processor for Programmable Switches☆13Dec 18, 2022Updated 3 years ago
- LZW Compressoion algorithm in verilog☆16Dec 19, 2013Updated 12 years ago
- Networking Template Library for Vivado HLS☆30Jul 12, 2020Updated 6 years ago
- Reducing P4 Language’s Voluminosity using Higher-Level Constructs☆15Oct 15, 2022Updated 4 years ago
- Radio Spectrum Viewer and Software Defined Radio in a cheap FPGA board☆21Apr 24, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Nitro E1 FPGA core☆13Apr 30, 2024Updated 2 years ago
- FPGA-based open-source network tester☆18Aug 5, 2014Updated 12 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆32Dec 10, 2021Updated 4 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆79Jan 29, 2017Updated 9 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆23Dec 17, 2025Updated 10 months ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- Implementation of Sobel Filter in Verilog☆30Mar 10, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆30Mar 27, 2025Updated last year
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- ☆27Feb 27, 2021Updated 5 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆72Jul 25, 2018Updated 8 years ago
- Blockchain Offload Engine☆17May 5, 2018Updated 8 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 8 years ago
- RISC-V by VectorBlox☆12Jul 19, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware Design of Ascon☆49Updated this week
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆18May 20, 2022Updated 4 years ago
- I2C Master Verilog module☆38Jun 1, 2025Updated last year
- ☆22Mar 30, 2023Updated 3 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- A Docker image for a software defined radio tuned to listen for Honeywell RF security sensors at 345Mhz☆19Mar 27, 2026Updated 7 months ago
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 4 years ago
- Implementations for draft-vanmook-intarea-ipv6-resolved-gateway☆11Jul 24, 2026Updated 3 months ago
- A history of PGP-related vulnerabilities☆24Jan 13, 2026Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- NTS proof of concept in Python☆10Jan 1, 2023Updated 3 years ago
- Portable NIC Architecture☆61Jun 2, 2026Updated 5 months ago
- etcd + exabgp☆28Jun 9, 2014Updated 12 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 6 years ago
- ☆14Feb 18, 2021Updated 5 years ago
- Borges - Python package & CLI for AS-to-Organization mapping: infers sibling ASNs from PeeringDB (LLM), WHOIS/AS2Org, and web signals (r…☆12Updated this week
- Async Fundamentals Workshopf or RustConf 2025☆15Sep 2, 2025Updated last year