Alternatives and similar repositories for Skill:

Users that are interested in Skill are comparing it to the libraries listed below

• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆76Updated 8 years ago
• unihd-cag / skillbridge
  A seamless python to Cadence Virtuoso Skill interface
  ☆189Updated 9 months ago
• ananthchellappa / SKILL
  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.
  ☆41Updated 3 months ago
• cdsdm / cdsdm
  Cadence Virtuoso Design Management System
  ☆33Updated 2 years ago
• KenKundert / psf_utils
  Read Spectre PSF files
  ☆56Updated 3 months ago
• cascode-labs / virtue
  A Python and SKILL Framework for Cadence Virtuoso
  ☆34Updated 11 months ago
• mfilmer / skill
  Useful Cadence skill scripts
  ☆14Updated 5 years ago
• cdsgit / cdsgit
  Cadence Virtuoso Git Integration written in SKILL++
  ☆153Updated 2 years ago
• ucb-art / BAG_framework
  ☆147Updated 2 years ago
• curtisma / VirtuosoToolboxMatlab
  MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System
  ☆28Updated 7 years ago
• fengqzHD / gmIdNeoKit
  Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
  ☆42Updated 4 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆55Updated 4 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆52Updated last week
• ucb-art / bag
  BAG framework
  ☆24Updated last month
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆53Updated 7 years ago
• dreoilin / pygmid
  A python3 gm/ID starter kit
  ☆46Updated 5 months ago
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆62Updated last year
• medwatt / gmid
  Python script for generating lookup tables for the gm/ID design methodology and much more ...
  ☆62Updated 10 months ago
• wulffern / aic2023
  Advanced integrated circuits 2023
  ☆30Updated 11 months ago
• bmurmann / Book-on-gm-ID-design
  Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
  ☆118Updated last week
• dwarning / VA-Models
  Verilog-A simulation models
  ☆64Updated last month
• efabless / foss-asic-tools
  FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…
  ☆79Updated 6 months ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆30Updated 2 years ago
• ALIGN-analoglayout / ALIGN-public
  ☆283Updated 2 months ago
• muhammadaldacher / Analog-Design-of-Bootstrapped-Switch
  This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…
  ☆10Updated 5 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆60Updated 2 weeks ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆46Updated 2 years ago
• MatthewLoveQUB / SKILL_Tools
  Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.
  ☆37Updated 4 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆69Updated 2 years ago