fabianschuiki / llhd-sim
The LLHD reference simulator.
☆38Updated 4 years ago
Alternatives and similar repositories for llhd-sim
Users that are interested in llhd-sim are comparing it to the libraries listed below
Sorting:
- A hardware compiler based on LLHD and CIRCT☆257Updated last year
- Verilator Porcelain☆47Updated last year
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- An HDL embedded in Rust.☆198Updated last year
- Logic circuit analysis and optimization☆37Updated 6 months ago
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆43Updated last month
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆412Updated 3 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆62Updated last week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Verilog AST☆21Updated last year
- Verilog parsing and generator crate.☆21Updated 5 years ago
- ☆102Updated 2 years ago
- ☆40Updated 3 years ago
- Time-sensitive affine types for predictable hardware generation☆143Updated 10 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆155Updated 3 weeks ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 4 months ago
- 21st century electronic design automation tools, written in Rust.☆30Updated 2 weeks ago
- ☆55Updated 2 years ago
- Native Rust implementation of the FST waveform format from GTKWave.☆12Updated last month
- RISCV Core written in Calyx☆16Updated 9 months ago
- Main page☆126Updated 5 years ago
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆33Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated last week
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated last week
- A nicer HDL.☆96Updated 8 years ago
- Debuggable hardware generator☆69Updated 2 years ago
- End-to-end synthesis and P&R toolchain☆83Updated last month