fabianschuiki / llhd-simLinks
The LLHD reference simulator.
☆39Updated 5 years ago
Alternatives and similar repositories for llhd-sim
Users that are interested in llhd-sim are comparing it to the libraries listed below
Sorting:
- A hardware compiler based on LLHD and CIRCT☆264Updated 5 months ago
- Verilator Porcelain☆49Updated 2 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆424Updated 3 years ago
- An HDL embedded in Rust.☆202Updated 2 years ago
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆102Updated this week
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆75Updated last week
- Logic circuit analysis and optimization☆45Updated 3 months ago
- Verilog AST☆21Updated 2 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Verilog parsing and generator crate.☆21Updated 5 years ago
- ☆104Updated 3 years ago
- ☆40Updated 4 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 months ago
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated last month
- Working draft of the proposed RISC-V Bitmanipulation extension☆216Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆143Updated 9 months ago
- Main page☆128Updated 5 years ago
- Time-sensitive affine types for predictable hardware generation☆147Updated last month
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- Fearless hardware design☆183Updated 3 months ago
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- A nicer HDL.☆98Updated 8 years ago
- A SystemVerilog language server based on the Slang library.☆76Updated this week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- End-to-end synthesis and P&R toolchain☆92Updated last week
- RISCV Core written in Calyx☆17Updated last year