fabianschuiki / llhd-sim
The LLHD reference simulator.
☆37Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for llhd-sim
- A hardware compiler based on LLHD and CIRCT☆250Updated last year
- Verilator Porcelain☆38Updated last year
- Read and write VCD (Value Change Dump) files in Rust☆41Updated 8 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Logic circuit analysis and optimization☆28Updated last month
- An HDL embedded in Rust.☆194Updated last year
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆41Updated last week
- ☆101Updated 2 years ago
- Verilog AST☆19Updated 11 months ago
- ☆52Updated 2 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆145Updated last week
- ☆41Updated 3 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆396Updated 2 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆28Updated this week
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- Native Rust implementation of the FST waveform format from GTKWave.☆12Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated last month
- A new Hardware Design Language that keeps you in the driver's seat☆70Updated this week
- A SystemVerilog source file pickler.☆51Updated last month
- A simple digital waveform viewer with vi-like key bindings.☆130Updated last year
- 21st century electronic design automation tools, written in Rust.☆12Updated 3 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆25Updated this week
- Rust RISC-V Virtual Machine☆88Updated 2 weeks ago
- Main page☆125Updated 4 years ago
- Rust Test Bench - write HDL tests in Rust.☆22Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- high-performance RTL simulator☆140Updated 5 months ago
- CHERI-RISC-V model written in Sail☆55Updated last week
- Hardware generator debugger☆71Updated 9 months ago