Alternatives and similar repositories for riscv-llvm:

Users that are interested in riscv-llvm are comparing it to the libraries listed below

• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆124Updated 4 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆149Updated last week
• Jonathan2251 / lbd
  ☆355Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated 11 months ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆611Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆150Updated 2 years ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆506Updated this week
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆699Updated 3 years ago
• riscv-non-isa / rvv-intrinsic-doc
  ☆318Updated 2 weeks ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆142Updated last year
• frasercrmck / llvm-leg
  ☆107Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆151Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 2 years ago
• rems-project / sail
  Sail architecture definition language
  ☆686Updated this week
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆256Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆183Updated 8 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆594Updated 2 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆731Updated last week
• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆408Updated 2 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆738Updated 6 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆477Updated 2 weeks ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆100Updated 6 years ago
• riscv-software-src / riscv-tests
  ☆947Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆704Updated this week
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆118Updated last year
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆113Updated 3 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆260Updated this week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated 2 weeks ago