bunnie / netv2-fpga-basic-overlay
Vivado design for basic NeTV2 FPGA with chroma-based overlay
☆20Updated 8 years ago
Alternatives and similar repositories for netv2-fpga-basic-overlay:
Users that are interested in netv2-fpga-basic-overlay are comparing it to the libraries listed below
- NeTV2 SoC based on LiteX☆16Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated this week
- IP submodules, formatted for easier CI integration☆29Updated last year
- USB 1.1 Device IP Core☆19Updated 7 years ago
- Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm☆33Updated 6 years ago
- understanding the tinyfpga bootloader☆24Updated 6 years ago
- ☆25Updated 6 years ago
- JTAG Hardware Abstraction Library☆36Updated last year
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆53Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆13Updated 4 years ago
- Small footprint and configurable video cores (Deprecated)☆71Updated 3 years ago
- A wishbone controlled PWM (audio) controller☆16Updated last year
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Open Source Hardware Designs for working with DisplayPort and intercepting AUX signals.☆16Updated 5 years ago
- FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display☆20Updated 7 years ago
- verilog FPGA code for NeTV☆62Updated 12 years ago
- Apio examples☆35Updated 3 weeks ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 3 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 10 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- ☆63Updated 4 years ago
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- Wishbone controlled I2C controllers☆46Updated 3 months ago
- Enigma in FPGA☆28Updated 5 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆47Updated last month