Alternatives and similar repositories for pynq:

Users that are interested in pynq are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆60Updated 5 months ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 4 months ago
• google / bottlerocket
  ☆109Updated 6 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 11 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated this week
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆51Updated 3 months ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• carlosedp / chisel-playground
  Chisel HDL example applications
  ☆30Updated 2 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆79Updated 4 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆89Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 7 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆118Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆119Updated 9 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago