Alternatives and similar repositories for fclkcfg

Users that are interested in fclkcfg are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated last week
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• pieter3d / simview
  ☆89Updated 3 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 5 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆94Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 8 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 10 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆172Updated this week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last year