ikwzm / fclkcfgLinks
FPGA Clock Configuration Device Driver for Linux
☆31Updated 3 weeks ago
Alternatives and similar repositories for fclkcfg
Users that are interested in fclkcfg are comparing it to the libraries listed below
Sorting:
- Naive Educational RISC V processor☆93Updated 2 months ago
- FuseSoC standard core library☆151Updated 3 weeks ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- ☆69Updated 5 months ago
- Yet Another RISC-V Implementation☆99Updated last year
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Verilog implementation of a RISC-V core☆133Updated 7 years ago
- ☆63Updated 7 years ago
- FPGA tool performance profiling☆104Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆170Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 9 months ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Updated 9 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ☆88Updated 2 months ago
- ☆59Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆132Updated 4 months ago
- The multi-core cluster of a PULP system.☆110Updated 2 months ago
- ☆43Updated 5 years ago