Alternatives and similar repositories for fclkcfg:

Users that are interested in fclkcfg are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated 3 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆82Updated 6 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• Digilent / digilent-vivado-scripts
  ☆69Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆92Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 3 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated last month
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆37Updated 3 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆113Updated 7 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 6 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆115Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆127Updated this week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆97Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆74Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago