Alternatives and similar repositories for IPXACT-Schema

Users that are interested in IPXACT-Schema are comparing it to the libraries listed below

• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆26Updated this week
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 4 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated last week
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated this week
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆61Updated 2 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated last month
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 6 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated 2 weeks ago
• muneebullashariff / PeakRDL-pdf
  Converts the SystemRDL data into pdf Register specification
  ☆13Updated last year
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 11 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆57Updated 9 months ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 8 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated last week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆39Updated 2 weeks ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆26Updated 8 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆69Updated 2 weeks ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 7 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆27Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆27Updated last year
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆35Updated 3 months ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆24Updated 4 years ago
• advanced-uvm / second_edition
  Code for the second edition of Advanced UVM.
  ☆27Updated 8 years ago