edaa-org / IPXACT-Schema

Related projects ⓘ

Alternatives and complementary repositories for IPXACT-Schema

• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆19Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆14Updated 8 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆21Updated last month
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated last week
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated last month
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆21Updated 3 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated last year
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆22Updated 4 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated this week
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 5 months ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆20Updated 8 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆16Updated 7 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆16Updated 11 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 8 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆36Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆23Updated 8 months ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated this week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆23Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆47Updated this week