Alternatives and similar repositories for IPXACT-Schema:

Users that are interested in IPXACT-Schema are comparing it to the libraries listed below

• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆22Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆50Updated 7 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated 6 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆24Updated 2 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated last month
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆37Updated 5 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆63Updated 2 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 9 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆23Updated 4 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆58Updated this week
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆35Updated 10 months ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 8 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 4 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆25Updated 8 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆60Updated last week
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆34Updated last month
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 5 years ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆36Updated 9 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆34Updated 5 months ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week