Alternatives and similar repositories for riscv-asic

Users that are interested in riscv-asic are comparing it to the libraries listed below

• ATaylorCEngFIET / Genesys_ZU_MIPI_PCAM
  Imaging application using MIPI and DisplayPort to process image
  ☆25Updated 5 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆11Updated 4 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 4 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆22Updated 6 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆42Updated 10 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• mballance / clusterv-soc
  Quad cluster of RISC-V cores with peripherals and local memory
  ☆24Updated 3 years ago
• ansonn / esl_systemc
  systemc建模相关
  ☆27Updated 11 years ago
• wzc810049078 / ZC-RISCV-CORE
  ZC RISCV CORE
  ☆13Updated 5 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• antmicro / openssd-nvme
  ☆29Updated 4 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• rgwan / AMBA
  Collection of IPs based on AMBA (AHB, APB, AXI) protocols
  ☆20Updated 8 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆20Updated 11 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• yasnakateb / PipelinedARM
  💎 A 32-bit ARM Processor Implementation in Verilog HDL
  ☆23Updated 3 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆18Updated 5 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆23Updated 2 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• FDU-ME-ARC / NVMeCHA
  ☆19Updated 4 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆18Updated last year
• openhwgroup / openhwgroup.org
  OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software desig…
  ☆18Updated 4 months ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆21Updated last year
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago