Alternatives and similar repositories for spat:

Users that are interested in spat are comparing it to the libraries listed below

• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 8 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 5 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆49Updated 5 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆22Updated 7 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆23Updated 3 years ago
• VLSIDA / puffery
  Tools for PUF analysis
  ☆11Updated 3 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆26Updated 3 years ago
• nils-wisiol / pypuf
  Cryptanalysis of Physically Unclonable Functions
  ☆86Updated 10 months ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• Tribler / software-based-PUF
  The first open source software-based Physically Unclonable Function (PUF) using off-the-shelf SRAM
  ☆94Updated this week
• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆18Updated 3 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆18Updated 5 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated 5 months ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆78Updated 3 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆16Updated 5 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated 7 months ago
• canaknesil / 4x4-apuf
  An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
  ☆15Updated 4 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• GMUCERG / LWC
  Development Package for the Hardware API for Lightweight Cryptography
  ☆16Updated last month
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆131Updated 2 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• vmarribas / VerMFi
  VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …
  ☆18Updated 5 years ago
• jens-na / VexRiscv-CCOPI
  Custom Coprocessor Interface for VexRiscv
  ☆9Updated 6 years ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆52Updated 2 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆31Updated last week
• raya4213 / VerilogCodeECC
  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
  ☆22Updated 8 years ago
• Chair-for-Security-Engineering / AGEMA
  Automated Generation of Masked Hardware
  ☆18Updated last year