Alternatives and similar repositories for spat

Users that are interested in spat are comparing it to the libraries listed below

• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 8 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆50Updated 5 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 5 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆23Updated 7 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 3 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• nils-wisiol / pypuf
  Cryptanalysis of Physically Unclonable Functions
  ☆87Updated 11 months ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆23Updated 3 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated 6 months ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆17Updated 5 years ago
• Tribler / software-based-PUF
  The first open source software-based Physically Unclonable Function (PUF) using off-the-shelf SRAM
  ☆95Updated last month
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• VLSIDA / puffery
  Tools for PUF analysis
  ☆11Updated 3 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 8 months ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 5 years ago
• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆18Updated 4 years ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆81Updated 3 years ago
• freecores / sha3
  SHA3 (KECCAK)
  ☆19Updated 10 years ago
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆20Updated 4 years ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon
  ☆22Updated last week
• ascon / ascon-hardware-sca
  NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks
  ☆17Updated 2 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆28Updated this week
• kmursi / ML_Attack_XOR_PUF
  The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…
  ☆17Updated 4 years ago
• canaknesil / 4x4-apuf
  An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
  ☆15Updated 4 years ago
• Secure-Embedded-Systems / Masked-AES-Implementation
  ☆23Updated 5 years ago
• AISyLab / side-channel-analysis-toolbox
  This is a project in which side-channel attacks are researched and developed.
  ☆46Updated 5 years ago
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆14Updated 2 years ago