Gabalo / RO_PUF
Ring Oscillator Physically Unclonable Funtion
☆18Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for RO_PUF
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆14Updated 4 years ago
- FPGA implementation of a physical unclonable function for authentication☆32Updated 7 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 6 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- Defense/Attack PUF Library (DA PUF Library)☆46Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- ☆17Updated last year
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 5 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆16Updated 2 years ago
- Elgamal's over Elliptic Curves☆19Updated 5 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 4 years ago
- True Random Number Generator core implemented in Verilog.☆72Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆46Updated 6 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- opensource crypto IP core☆26Updated 4 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆81Updated 2 years ago
- few python scripts to clone all IP cores from opencores.org☆18Updated 10 months ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆17Updated 7 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆37Updated 7 years ago
- VHDL Implementation of AES Algorithm☆72Updated 3 years ago
- Advanced encryption standard implementation in verilog.☆27Updated 2 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆16Updated 8 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- AES加密解密算法的Verilog实现☆60Updated 8 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆29Updated 4 months ago