Gabalo / RO_PUFLinks
Ring Oscillator Physically Unclonable Funtion
☆23Updated 3 years ago
Alternatives and similar repositories for RO_PUF
Users that are interested in RO_PUF are comparing it to the libraries listed below
Sorting:
- FPGA implementation of a physical unclonable function for authentication☆32Updated 8 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆15Updated 4 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 5 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 5 years ago
- Defense/Attack PUF Library (DA PUF Library)☆50Updated 5 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 5 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 5 years ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- Verilog Hardware Design of Ascon☆22Updated last week
- FPGA implementation of Chinese SM4 encryption algorithm.☆53Updated 7 years ago
- ☆20Updated 2 years ago
- few python scripts to clone all IP cores from opencores.org☆22Updated last year
- Tools for PUF analysis☆11Updated 3 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆21Updated 3 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Updated 7 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- C++ and Verilog to implement AES128☆22Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- A demo system for Ibex including debug support and some peripherals☆67Updated 2 weeks ago
- VHDL Implementation of AES Algorithm☆81Updated 3 years ago
- The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…☆17Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago