Alternatives and similar repositories for fpga_puf

Users that are interested in fpga_puf are comparing it to the libraries listed below

• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆205Updated 2 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆90Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆148Updated 5 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 8 months ago
• olofk / corescore
  CoreScore
  ☆167Updated 3 weeks ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆117Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆123Updated 4 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆85Updated last week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆49Updated 2 years ago
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆268Updated last week
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 6 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆142Updated 2 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆185Updated last year
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆206Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated last year
• pieter3d / simview
  ☆87Updated last month
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆92Updated 4 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆80Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆186Updated last month
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 months ago
• ldoolitt / vhd2vl
  ☆137Updated 11 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆209Updated last year