stnolting / fpga_puf
Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
☆130Updated 2 years ago
Alternatives and similar repositories for fpga_puf:
Users that are interested in fpga_puf are comparing it to the libraries listed below
- FuseSoC standard core library☆128Updated last month
- Naive Educational RISC V processor☆79Updated 5 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆75Updated 3 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆138Updated 2 years ago
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆178Updated 2 months ago
- Control and Status Register map generator for HDL projects☆113Updated last month
- Fabric generator and CAD tools☆162Updated last month
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆159Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- VHDL library 4 FPGAs☆175Updated this week
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆132Updated this week
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆71Updated last week
- ☆77Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆229Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆61Updated this week
- FPGA tool performance profiling☆102Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆154Updated last week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆114Updated 3 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆111Updated 5 months ago
- Playing around with Formal Verification of Verilog and VHDL☆55Updated 4 years ago
- Vivado build system☆68Updated 3 months ago
- Mathematical Functions in Verilog☆91Updated 4 years ago