Praneshss / Modeling_of_APUF_CompositionsLinks
Python Code and Dataset for different PUFs
☆18Updated 4 years ago
Alternatives and similar repositories for Modeling_of_APUF_Compositions
Users that are interested in Modeling_of_APUF_Compositions are comparing it to the libraries listed below
Sorting:
- The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…☆17Updated 4 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- VHDL Implementation of AES Algorithm☆84Updated 4 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆11Updated 4 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 5 years ago
- Defense/Attack PUF Library (DA PUF Library)☆50Updated 5 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆12Updated 5 years ago
- Repository to store all design and testbench files for Senior Design☆19Updated 5 years ago
- AES hardware engine for Xilinx Zynq platform☆32Updated 4 years ago
- ☆47Updated 4 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- Implemented The UART with FIFO☆14Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 3 months ago
- Configurable AES-GCM IP (128, 192, 256 bits)☆36Updated last week
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- PYNQ Composabe Overlays☆73Updated last year
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Updated 9 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 5 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆40Updated 8 years ago
- ☆69Updated last month
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆60Updated 5 months ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- A compact, configurable RISC-V core☆11Updated last month
- Flip flop setup, hold & metastability explorer tool☆48Updated 2 years ago
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆21Updated 3 years ago
- Python interface to PCIE☆40Updated 7 years ago