Alternatives and similar repositories for Modeling_of_APUF_Compositions

Users that are interested in Modeling_of_APUF_Compositions are comparing it to the libraries listed below

• kmursi / ML_Attack_XOR_PUF
  The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…
  ☆20Updated 5 years ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆91Updated 4 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆24Updated 8 years ago
• newaetech / CW305-Arm-DesignStart
  Instruction and files for porting Arm DesignStart to CW305.
  ☆16Updated 2 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 8 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• adnanbaysal / TRNG-with-Ring-Oscillators-in-Verilog
  A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
  ☆11Updated 5 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆12Updated 5 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆55Updated 5 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆22Updated 5 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated last year
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆52Updated 4 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆32Updated 4 years ago
• BLu85 / AES-GCM-128-192-256-bits
  Configurable AES-GCM IP (128, 192, 256 bits)
  ☆38Updated 5 months ago
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆45Updated 8 years ago
• A-suozhang / Verilog_Uart_With_Fifo
  Implemented The UART with FIFO
  ☆15Updated 6 years ago
• karanahujax / PUF
  Cryptographic Key Generation from PUF Data
  ☆23Updated 6 years ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆41Updated 8 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆19Updated 6 years ago
• xyzxinyizhang / FPGA-SFP-communication-with-Aurora
  ☆20Updated 7 years ago
• aneeshkandi14 / ascon-hw-public
  ☆22Updated last year
• SpinalHDL / VexRiscvSocSoftware
  ☆27Updated 4 years ago
• Xilinx / bootgen
  bootgen source code
  ☆57Updated 2 months ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 6 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆173Updated 4 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆43Updated 3 years ago
• coltonshane / SSD_Test
  SSD test project using Zynq Ultrascale+ bare metal NVMe.
  ☆22Updated 4 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆74Updated last year
• Avnet / bdf
  Avnet Board Definition Files
  ☆140Updated last month
• fpgadeveloper / microzed-axi-dma
  Demonstration of the AXI DMA engine on the MicroZed
  ☆26Updated 4 years ago