Alternatives and similar repositories for logic2

Users that are interested in logic2 are comparing it to the libraries listed below

• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last month
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆100Updated 2 weeks ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 2 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆51Updated 2 weeks ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆90Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated 2 weeks ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆61Updated last month
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆105Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 8 months ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 2 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆66Updated this week
• vmunoz82 / eda_tools
  A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …
  ☆46Updated 2 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆94Updated 4 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• SpinalHDL / SpinalDoc-RTD
  The sources of the online SpinalHDL doc
  ☆29Updated 2 weeks ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆61Updated 2 months ago
• Nic30 / d3-hwschematic
  D3.js and ELK based schematic visualizer
  ☆105Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆38Updated 2 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆48Updated 2 years ago