dkilfoyle / logic2
Digital Logic Simulator
☆31Updated 3 years ago
Alternatives and similar repositories for logic2
Users that are interested in logic2 are comparing it to the libraries listed below
Sorting:
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Visual Simulation of Register Transfer Logic☆98Updated 2 months ago
- Debuggable hardware generator☆69Updated 2 years ago
- Digital Circuit rendering engine☆39Updated last year
- ☆40Updated last month
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆42Updated 4 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆56Updated last week
- Another tiny RISC-V implementation☆55Updated 3 years ago
- CMake based hardware build system☆19Updated this week
- SpinalHDL Hardware Math Library☆85Updated 10 months ago
- Raptor end-to-end FPGA Compiler and GUI☆78Updated 5 months ago
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- RISC-V Nox core☆62Updated last month
- D3.js based wave (signal) visualizer☆61Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Export netlists from Yosys to DigitalJS☆50Updated last year
- IRSIM switch-level simulator for digital circuits☆34Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆91Updated 8 months ago
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆21Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆46Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- An automatic clock gating utility☆47Updated last month
- HTML & Js based VCD viewer☆60Updated 4 years ago
- A pipelined RISC-V processor☆55Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 4 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago