dkilfoyle / logic2Links
Digital Logic Simulator
☆34Updated 4 years ago
Alternatives and similar repositories for logic2
Users that are interested in logic2 are comparing it to the libraries listed below
Sorting:
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last month
- Digital Circuit rendering engine☆39Updated 6 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- D3.js based wave (signal) visualizer☆67Updated 5 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆66Updated 3 months ago
- Visual Simulation of Register Transfer Logic☆110Updated 5 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Updated 2 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- Export netlists from Yosys to DigitalJS☆57Updated 2 weeks ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Raptor end-to-end FPGA Compiler and GUI☆94Updated last year
- D3.js and ELK based schematic visualizer☆114Updated last year
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- mantle library☆44Updated 3 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Example of how to use UVM with Verilator☆33Updated 2 months ago
- Another tiny RISC-V implementation☆64Updated 4 years ago
- Fine Grain FPGA Overlay Architecture and Tools☆28Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- SpinalHDL Hardware Math Library☆94Updated last year
- OpenFPGA☆34Updated 7 years ago
- KLayout technology files for ASAP7 FinFET educational process☆24Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆48Updated 2 years ago