dkilfoyle / logic2Links
Digital Logic Simulator
☆31Updated 4 years ago
Alternatives and similar repositories for logic2
Users that are interested in logic2 are comparing it to the libraries listed below
Sorting:
- Small SERV-based SoC primarily for OpenMPW tapeout☆46Updated 2 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆61Updated last year
- Debuggable hardware generator☆69Updated 2 years ago
- D3.js based wave (signal) visualizer☆63Updated last year
- Visual Simulation of Register Transfer Logic☆99Updated 5 months ago
- SpinalHDL Hardware Math Library☆89Updated last year
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆46Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated 2 weeks ago
- WAL enables programmable waveform analysis.☆155Updated 2 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆64Updated last week
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆61Updated 2 months ago
- Raptor end-to-end FPGA Compiler and GUI☆84Updated 8 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- CMake based hardware build system☆30Updated 2 weeks ago
- ☆19Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- Drawio => VHDL and Verilog☆56Updated last year
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆97Updated 5 months ago
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- D3.js and ELK based schematic visualizer☆104Updated last year
- Dual-issue RV64IM processor for fun & learning☆63Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆79Updated last year
- Mathematical Functions in Verilog☆93Updated 4 years ago
- Digital Circuit rendering engine☆39Updated last week
- The sources of the online SpinalHDL doc☆29Updated 3 weeks ago
- An implementation of RISC-V☆38Updated last month
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago