vmunoz82 / eda_toolsLinks
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
☆43Updated last year
Alternatives and similar repositories for eda_tools
Users that are interested in eda_tools are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆57Updated this week
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- A pipelined RISC-V processor☆57Updated last year
- ☆41Updated 2 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆105Updated 10 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Virtual Development Board☆60Updated 3 years ago
- Example of how to get started with olofk/fusesoc.☆17Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆92Updated 8 months ago
- SystemVerilog frontend for Yosys☆117Updated last week
- ☆79Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- Spen's Official OpenOCD Mirror☆50Updated 2 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆77Updated 11 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆42Updated this week
- ☆69Updated 9 months ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆54Updated 2 years ago
- FPGA examples on Google Colab☆22Updated last year
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆38Updated 3 weeks ago