Alternatives and similar repositories for tee-hardware:

Users that are interested in tee-hardware are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆35Updated last year
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆15Updated 3 weeks ago
• pulp-platform / hci
  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  ☆13Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• ucb-bar / midas-examples
  Simple MIDAS Examples
  ☆12Updated 6 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• ccelio / riscv-hpmcounters
  A simple utility for doing RISC-V HPM perf monitoring.
  ☆14Updated 7 years ago
• shenyaming / riscv-fpga
  Share JTAG chain within RISCV core and Xilinx FPGA.
  ☆9Updated 5 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆16Updated 2 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated last month
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 3 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 4 months ago
• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆35Updated 2 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆31Updated 11 months ago
• asinghani / crypto-accelerator-chip
  Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…
  ☆22Updated 4 years ago
• riscveval / Rocket-Chip
  ☆22Updated 7 years ago
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆27Updated 8 months ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆20Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated 7 months ago
• RSPwFPGAs / virtio-fpga
  A platform for emulating Virtio devices with FPGAs
  ☆25Updated 4 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 4 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year