Alternatives and similar repositories for tee-hardware

Users that are interested in tee-hardware are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• XUANTIE-RV / tvm
  TVM for chips base on Xuantie CPU, an open deep learning compiler stack.
  ☆30Updated last year
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 weeks ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 7 months ago
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 9 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆35Updated 5 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 8 months ago
• riscvarchive / riscv-zfinx
  ☆12Updated last year
• pulp-platform / hci
  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  ☆14Updated this week
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆21Updated 4 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆42Updated 5 years ago
• AlSaqr-platform / he-soc
  ☆32Updated 2 weeks ago
• asinghani / crypto-accelerator-chip
  Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…
  ☆23Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆14Updated 7 months ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆43Updated 4 months ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆15Updated last year
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆27Updated 4 months ago
• anishathalye / bin2coe
  A tool to convert binary files to COE files 💫
  ☆16Updated last month
• b224hisl / rioschip
  ☆33Updated 2 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• Nuclei-Software / nuclei-ai-library
  Nuclei AI Library Optimized For RISC-V Vector
  ☆13Updated last month
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago