TinyTapeout / tinytapeout-mpw7Links
TinyTapeout-01 submission repo
☆32Updated 3 years ago
Alternatives and similar repositories for tinytapeout-mpw7
Users that are interested in tinytapeout-mpw7 are comparing it to the libraries listed below
Sorting:
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆111Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated 2 weeks ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- ☆71Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 4 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- ☆38Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 2 weeks ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Repo to help explain the different options users have for packaging.☆18Updated 3 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆102Updated 2 years ago
- ☆34Updated 4 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- Submission template for Tiny Tapeout 03☆20Updated 2 years ago
- Virtual Development Board☆64Updated 4 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆64Updated 2 months ago
- Documenting the Lattice ECP5 bit-stream format.☆56Updated 2 years ago
- A Risc-V SoC for Tiny Tapeout☆43Updated this week
- SAR ADC on tiny tapeout☆43Updated 10 months ago
- ☆20Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆17Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆38Updated 3 years ago