Alternatives and similar repositories for tinytapeout-mpw7

Users that are interested in tinytapeout-mpw7 are comparing it to the libraries listed below

• rain-neuromorphics / torchmx

  View on GitHub
  PyTorch Quantization Framework For OCP MX Datatypes.
  ☆16May 30, 2025Updated 8 months ago
• MichaelBell / tinyQV

  View on GitHub
  A Risc-V SoC for Tiny Tapeout
  ☆48Dec 2, 2025Updated 2 months ago
• mattvenn / wokwi-verilog-gds-test

  View on GitHub
  ☆55Oct 24, 2022Updated 3 years ago
• wallento / cocotbext-wishbone

  View on GitHub
  ☆20Feb 3, 2026Updated last week
• openhwgroup / riscv_vm

  View on GitHub
  Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board
  ☆15Nov 16, 2022Updated 3 years ago
• christoph-weiser / mpw7

  View on GitHub
  Efabless mpw7 submission
  ☆14May 6, 2024Updated last year
• kumarrishav14 / AMBA_APB

  View on GitHub
  To design test bench of the APB protocol
  ☆18Dec 30, 2020Updated 5 years ago
• zhuzilin / pytorch-malloc

  View on GitHub
  An external memory allocator example for PyTorch.
  ☆16Aug 10, 2025Updated 6 months ago
• Mecrisp / Nandland-RISC-V

  View on GitHub
  RISC-V Playground on Nandland Go
  ☆16Mar 2, 2023Updated 2 years ago
• sfmth / ibnalhaytham

  View on GitHub
  32-bit RISC-V based processor with memory controler
  ☆16Sep 2, 2022Updated 3 years ago
• efabless / caravel_mpw-one

  View on GitHub
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Feb 22, 2022Updated 3 years ago
• mortie / rv32i-logisim-cpu

  View on GitHub
  Implementation of RV32I in Logisim-evolution.
  ☆26Sep 19, 2023Updated 2 years ago
• westonb / sky130-analog

  View on GitHub
  Analog and power building blocks for sky130 pdk
  ☆22Mar 3, 2021Updated 4 years ago
• antmicro / verilator-old-archived

  View on GitHub
  ☆21Mar 5, 2023Updated 2 years ago
• rob-ng15 / PAWS

  View on GitHub
  PLEASE MOVE TO PAWSv2
  ☆16Feb 2, 2022Updated 4 years ago
• iic-jku / SKY130_SAR-ADC1

  View on GitHub
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆51Mar 13, 2025Updated 11 months ago
• zeeshanrafique23 / RV32I-Logisim

  View on GitHub
  RV32I single cycle simulation on open-source software Logisim.
  ☆21Oct 8, 2022Updated 3 years ago
• efabless / caravel-lite

  View on GitHub
  ☆17Nov 4, 2024Updated last year
• samlittlewood / caravel_carrier

  View on GitHub
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Sep 24, 2021Updated 4 years ago
• clairexen / picorv

  View on GitHub
  PicoRV
  ☆43Feb 19, 2020Updated 5 years ago
• zxmarcos / huedeon-gpu

  View on GitHub
  FPGA GPU design for DE1-SoC
  ☆73Dec 27, 2021Updated 4 years ago
• krishnan-r / Logisim-RISC-Processor

  View on GitHub
  A 32-Bit RISC Processor implemented on Logisim along with a python based assembler.
  ☆17Nov 4, 2017Updated 8 years ago
• salcanmor / SRAM-tester-for-Cmod-A7-35T

  View on GitHub
  Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T
  ☆20Nov 25, 2018Updated 7 years ago
• mmicko / cross-fpga

  View on GitHub
  Cross compile FPGA tools
  ☆21Jan 4, 2021Updated 5 years ago
• ARNTM / Todo_TELEMATICA

  View on GitHub
  ☆12May 21, 2024Updated last year
• dan-rodrigues / caravel_vdp_lite

  View on GitHub
  ☆20Dec 23, 2020Updated 5 years ago
• alexforencich / dma-bench

  View on GitHub
  ☆27Jun 12, 2022Updated 3 years ago
• hossein1387 / BARVINN

  View on GitHub
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆94Jan 5, 2025Updated last year
• TinyTapeout / tt03-submission-template

  View on GitHub
  Submission template for Tiny Tapeout 03
  ☆22Sep 20, 2023Updated 2 years ago
• Toms42 / logisim-RISC-V-CPU

  View on GitHub
  ☆21Jun 2, 2017Updated 8 years ago
• laurentc2 / ASAP7_for_KLayout

  View on GitHub
  KLayout technology files for ASAP7 FinFET educational process
  ☆24Feb 5, 2023Updated 3 years ago
• Ravenslofty / blog

  View on GitHub
  The Critical Path - a rambly FPGA blog
  ☆51Sep 4, 2020Updated 5 years ago
• 1adrianb / expert-binary-networks

  View on GitHub
  Code for High-Capacity Expert Binary Networks (ICLR 2021).
  ☆27Dec 3, 2021Updated 4 years ago
• openXC7 / openXC7-snap

  View on GitHub
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆29Jul 10, 2024Updated last year
• fredrequin / fpga_1943

  View on GitHub
  Verilog re-implementation of the famous CAPCOM arcade game
  ☆29Jan 25, 2019Updated 7 years ago
• keithallatt / logisim-cpu

  View on GitHub
  4 Bit CPU build in Logisim Evolution, with Compiler and IDE.
  ☆31Nov 2, 2020Updated 5 years ago
• TinyTapeout / xschem-viewer

  View on GitHub
  Online viewer of Xschem schematic files
  ☆28Dec 14, 2025Updated 2 months ago
• bitbank2 / Pocket_CO2

  View on GitHub
  A CH32V003 low cost pocket CO2 sensor
  ☆29Jun 20, 2023Updated 2 years ago
• GATECH-EIC / DNN-Chip-Predictor

  View on GitHub
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Oct 1, 2022Updated 3 years ago