Alternatives and similar repositories for tinytapeout-mpw7

Users that are interested in tinytapeout-mpw7 are comparing it to the libraries listed below

• dan-rodrigues / caravel_vdp_lite
  ☆20Updated 4 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last month
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• efabless / clear
  ☆70Updated 10 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆95Updated last month
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆36Updated 2 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 7 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆48Updated last month
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 9 months ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• MichaelBell / tinyQV
  A Risc-V SoC for Tiny Tapeout
  ☆19Updated 4 months ago
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆18Updated last week
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 5 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 4 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆62Updated 2 years ago
• hdl / packages
  Repo to help explain the different options users have for packaging.
  ☆17Updated 3 years ago
• efabless / caravel_board
  ☆36Updated 8 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated last week
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated this week
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆47Updated last year
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated last week
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 3 years ago