Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
☆28Jan 15, 2020Updated 6 years ago
Alternatives and similar repositories for matrix-creator-fpga
Users that are interested in matrix-creator-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project acquires the PDM (Pulse Density Modulation) microphone signal using SPI with software CIC(Cascaded Integrator-Comb) filter a…☆14Aug 19, 2017Updated 9 years ago
- Explanation of FPGA code for 8 PDM microphones in Matrix Creator☆15Nov 9, 2020Updated 5 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 11 years ago
- ☆15Nov 28, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆13Feb 13, 2021Updated 5 years ago
- ☆11Oct 18, 2024Updated last year
- ☆18Sep 16, 2020Updated 5 years ago
- ☆12Jan 12, 2019Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆77Jun 16, 2022Updated 4 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 9 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- AT command server written in C++☆12Aug 2, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Synthesizable FIR filters in VHDL☆15Jul 19, 2019Updated 7 years ago
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆14May 23, 2019Updated 7 years ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Simple projects with the CYC1000 FPGA board☆11Apr 21, 2020Updated 6 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆29Apr 1, 2020Updated 6 years ago
- Blackwire SpinalHDL components implementing WireGuard primitives☆16Aug 16, 2023Updated 3 years ago
- ☆12Sep 8, 2017Updated 8 years ago
- ☆26Mar 27, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆17Aug 16, 2023Updated 3 years ago
- % Phased Array Antenna, Radiation Pattern and Array Configuration % Phased array consisting of N lined up individual isotropic antennas …☆15Oct 28, 2017Updated 8 years ago
- The repository is created to support a Capstone project on the topic of "Study and Implementation of Sound Source Localization Techniques…☆13Apr 27, 2021Updated 5 years ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- Collection of miscellaneous tools for PDM signals generation, acquisition and decoding☆47Nov 22, 2019Updated 6 years ago
- ☆15Jul 25, 2017Updated 9 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Jan 23, 2016Updated 10 years ago
- This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware.☆16Nov 9, 2017Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)☆31Jan 25, 2016Updated 10 years ago
- Thinned Array Beampattern Synthesis by Iterative Soft-Thresholding based Optimization Algorithms☆12Nov 19, 2015Updated 10 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- 使用GEC6818(ARM开发板)以及Linux操作系统来设计一个可以实现动感相册/监控/音乐播放器功能且UI友好，人机交互性高的智能家居系统。☆15Mar 13, 2023Updated 3 years ago