craymichael / CBP-16-Simulation
Branch predictor simulation, analysis, and Python compatibility for the 5th Championship Branch Prediction in 2016 (CBP-16)
☆21Updated 2 years ago
Alternatives and similar repositories for CBP-16-Simulation:
Users that are interested in CBP-16-Simulation are comparing it to the libraries listed below
- ☆80Updated this week
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Wrapper for Rocket-Chip on FPGAs☆132Updated 2 years ago
- An integrated CGRA design framework☆87Updated last month
- A Study of the SiFive Inclusive L2 Cache☆61Updated last year
- some knowleage about SystemC/TLM etc.☆24Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆194Updated last month
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆20Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆123Updated last week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 9 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- ☆147Updated 2 weeks ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- Unit tests generator for RVV 1.0☆82Updated 3 weeks ago
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆163Updated last week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆92Updated last week
- Source Code for training and evaluating BranchNet models for branch prediction☆33Updated 4 years ago
- Modeling Architectural Platform☆185Updated this week
- ☆26Updated 8 years ago
- Championship Branch Prediction 2025☆40Updated 3 weeks ago
- A matrix extension proposal for AI applications under RISC-V architecture☆138Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆149Updated 2 years ago
- ☆60Updated 2 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆258Updated last month
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆195Updated 2 weeks ago