ramisheikh / cbp2025
Championship Branch Prediction 2025
☆33Updated last week
Alternatives and similar repositories for cbp2025:
Users that are interested in cbp2025 are comparing it to the libraries listed below
- Advanced Architecture Labs with CVA6☆55Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆88Updated last month
- The OpenPiton Platform☆28Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated this week
- RISC-V Matrix Specification☆19Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆50Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Unit tests generator for RVV 1.0☆79Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated last year
- Spike with a coherence supported cache model☆13Updated 8 months ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆67Updated 6 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆40Updated 2 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- ☆32Updated last week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Branch Predictor Optimization for BlackParrot☆15Updated last year
- Championship Value Prediction (CVP) simulator.☆16Updated 4 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 9 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆89Updated this week
- ☆32Updated 4 years ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆21Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago