ramisheikh / cbp2025View external linksLinks
Championship Branch Prediction 2025
☆67May 19, 2025Updated 8 months ago
Alternatives and similar repositories for cbp2025
Users that are interested in cbp2025 are comparing it to the libraries listed below
Sorting:
- The simulator for the Next-Generation Championship in Branch Prediction (CBP-NG)☆22Updated this week
- Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5☆30Updated this week
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆16Sep 1, 2023Updated 2 years ago
- Implementation of TAGE Branch Predictor - currently considered state of the art☆52Sep 6, 2014Updated 11 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated 8 months ago
- The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their application…☆31Apr 23, 2025Updated 9 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 3 months ago
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆669Feb 1, 2026Updated last week
- ☆33Apr 8, 2020Updated 5 years ago
- [TACO 2024] A hardware prefetching framework employing Tyche, a hardware prefetcher designed for indirect memory access patterns.☆25Apr 15, 2024Updated last year
- Source Code for training and evaluating BranchNet models for branch prediction☆41Dec 1, 2020Updated 5 years ago
- The Unified TileLink Memory Subsystem Tester for XiangShan☆12Jan 7, 2026Updated last month
- Branch predictor simulation, analysis, and Python compatibility for the 5th Championship Branch Prediction in 2016 (CBP-16)☆20Mar 9, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- ☆26Mar 19, 2021Updated 4 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆92Oct 17, 2025Updated 3 months ago
- Software artifacts for "UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance" (…☆11Dec 27, 2021Updated 4 years ago
- SYSU-ARCH is a LAB that focuses on the use and extending of simulators.☆10Dec 19, 2022Updated 3 years ago
- SoC for muntjac☆12Jun 18, 2025Updated 7 months ago
- ☆14Feb 2, 2026Updated last week
- ☆15Feb 5, 2026Updated last week
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- Baremetal Backtracing on RISC-V☆16Jun 22, 2021Updated 4 years ago
- ☆20Nov 27, 2023Updated 2 years ago
- Modeling Architectural Platform☆219Updated this week
- ☆12Nov 27, 2021Updated 4 years ago
- Extremely Simple Microbenchmarks☆39May 23, 2018Updated 7 years ago
- Memory consistency model checking and test generation library.☆16Oct 14, 2016Updated 9 years ago
- Readings in Computer Architectures☆17Dec 21, 2025Updated last month
- Basic Common Modules☆46Dec 13, 2025Updated 2 months ago
- A C version of Branch Predictor Simulator☆17Jul 10, 2024Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- ☆31Updated this week
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 7 months ago
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Nov 23, 2023Updated 2 years ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆517Apr 8, 2024Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Jun 22, 2024Updated last year
- A simple CPU ray tracer written in Rust☆22Mar 10, 2023Updated 2 years ago
- Loongarch Emulator☆19Mar 14, 2025Updated 11 months ago