ramisheikh / cbp2025Links
Championship Branch Prediction 2025
☆45Updated last month
Alternatives and similar repositories for cbp2025
Users that are interested in cbp2025 are comparing it to the libraries listed below
Sorting:
- Advanced Architecture Labs with CVA6☆62Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Unit tests generator for RVV 1.0☆88Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆85Updated 9 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated 2 weeks ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆116Updated this week
- Source Code for training and evaluating BranchNet models for branch prediction☆35Updated 4 years ago
- ☆86Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆52Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆91Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- The official repository for the gem5 resources sources.☆72Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆101Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- The Task Parallel System Composer (TaPaSCo)☆109Updated last month
- Branch predictor simulation framework for the Last-Level Branch Predictor☆24Updated 10 months ago
- CGRA framework with vectorization support.☆32Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- ☆26Updated 8 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆88Updated last week
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆78Updated last year
- gem5 Tips & Tricks☆70Updated 5 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago