Alternatives and similar repositories for Verilog-Hdl-Format

Users that are interested in Verilog-Hdl-Format are comparing it to the libraries listed below

• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆382Updated 2 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆153Updated 3 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆62Updated 2 years ago
• RongyeL / EasyAXI
  ☆50Updated last month
• RainEggplant / vscode-verilog-integration
  使用 VSCode 舒适地开发 Verilog
  ☆33Updated 4 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆219Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆148Updated 6 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆117Updated last year
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆67Updated 3 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆147Updated 3 weeks ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆159Updated last year
• xupsh / Digital-Design-Lab
  ☆221Updated 4 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆209Updated 11 months ago
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• shun6-6 / Tri_Eth_UDP_pro_stack
  基于FPGA的三速以太网UDP协议栈设计
  ☆27Updated last year
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆51Updated 11 months ago
• ysyx-ta / ysyx-slides
  ☆30Updated 3 weeks ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• BIGWJZ / VLSI-DSP-Review
  ☆70Updated 4 years ago
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆22Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆97Updated 2 weeks ago
• jerrylioon / Solutions-to-HDLbits-Verilog-sets
  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
  ☆90Updated last year
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆47Updated last year
• WangXuan95 / FPGA-SDcard-Reader
  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
  ☆305Updated last year
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago