1391074994 / Verilog-Hdl-FormatLinks
Verilog Hdl Format
☆26Updated 3 months ago
Alternatives and similar repositories for Verilog-Hdl-Format
Users that are interested in Verilog-Hdl-Format are comparing it to the libraries listed below
Sorting:
- 在vscode上的数字设计开发插件☆386Updated 2 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆65Updated 2 years ago
- AXI协议规范中 文翻译版☆163Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆110Updated 3 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆164Updated last year
- ☆30Updated 3 months ago
- ☆149Updated 3 weeks ago
- ☆69Updated 3 weeks ago
- 使用 VSCode 舒适地开发 Verilog☆34Updated 5 years ago
- ☆156Updated this week
- SpinalHDL-tutorial based on Jupyter Notebook☆140Updated last year
- OpenXuantie - OpenE902 Core☆156Updated last year
- ☆206Updated 5 months ago
- ☆87Updated last week
- ☆222Updated 4 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- automatic-verilog based on vimscript☆272Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- ☆83Updated 5 months ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆254Updated 2 years ago
- ☆65Updated 5 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆210Updated 3 months ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆150Updated 6 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆123Updated 3 years ago
- Vivado诸多IP，包括图像处理等☆230Updated last year
- ☆144Updated 4 years ago
- ☆67Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- ☆64Updated 3 years ago