Alternatives and similar repositories for -TAGE-based-Predictor-Verilog-Code

Users that are interested in -TAGE-based-Predictor-Verilog-Code are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆125Updated this week
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆68Updated 2 years ago
• Jpz-sdju / trinity
  ☆32Updated 6 months ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆223Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• OSCPU / chisel-playground
  ☆71Updated last week
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆77Updated 2 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 8 months ago
• RV-BOSC / OpenNoC
  ☆220Updated 7 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 4 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆226Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆161Updated 11 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆194Updated last year
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆67Updated 8 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆140Updated 11 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 8 months ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago