Alternatives and similar repositories for -TAGE-based-Predictor-Verilog-Code

Users that are interested in -TAGE-based-Predictor-Verilog-Code are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆97Updated last week
• OSCPU / ysyxSoC
  ☆86Updated last week
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• OSCPU / yosys-sta
  ☆78Updated 4 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆65Updated last year
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆151Updated 6 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆178Updated 10 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆29Updated 3 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆206Updated 2 months ago
• OSCPU / chisel-playground
  ☆67Updated 6 months ago
• RV-BOSC / OpenNoC
  ☆184Updated 2 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated last week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆148Updated this week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• Jpz-sdju / trinity
  ☆25Updated 3 weeks ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆30Updated last month
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆66Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆64Updated last week
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 4 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 3 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 3 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆108Updated 6 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago