Alternatives and similar repositories for -TAGE-based-Predictor-Verilog-Code

Users that are interested in -TAGE-based-Predictor-Verilog-Code are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆106Updated this week
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆67Updated last year
• OSCPU / ysyxSoC
  ☆88Updated 3 weeks ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• OSCPU / yosys-sta
  ☆83Updated 6 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆212Updated 4 months ago
• Jpz-sdju / trinity
  ☆30Updated 2 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU / chisel-playground
  ☆67Updated 8 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆30Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆70Updated last week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated last month
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 5 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆26Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆215Updated 2 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆181Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆159Updated last week
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆153Updated 8 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆309Updated last month
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 6 months ago