regymm / buildrootLinks
buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
☆27Updated last year
Alternatives and similar repositories for buildroot
Users that are interested in buildroot are comparing it to the libraries listed below
Sorting:
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆41Updated last month
- FLIX-V: FPGA, Linux and RISC-V☆42Updated last year
- Exploring gate level simulation☆58Updated 2 months ago
- ☆41Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- A pipelined RISC-V processor☆57Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆94Updated last week
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆48Updated 2 weeks ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆79Updated last year
- Experiments with Yosys cxxrtl backend☆49Updated 5 months ago
- A design for TinyTapeout☆16Updated 2 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆15Updated last year
- Linux capable RISC-V SoC designed to be readable and useful.☆147Updated 3 weeks ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- Doom classic port to lightweight RISC‑V☆94Updated 2 years ago
- ☆15Updated last month
- VexRiscV system with GDB-Server in Hardware☆21Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆54Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated 8 months ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆69Updated 2 weeks ago