regymm / buildroot
buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
☆26Updated 11 months ago
Alternatives and similar repositories for buildroot:
Users that are interested in buildroot are comparing it to the libraries listed below
- FLIX-V: FPGA, Linux and RISC-V☆41Updated last year
- Doom classic port to lightweight RISC‑V☆90Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 11 months ago
- Container for compiling LiteX HDL FPGA designs using the free OpenXC7 tool chain and GitHub code spaces☆25Updated last year
- Exploring gate level simulation☆56Updated this week
- Naive Educational RISC V processor☆80Updated 6 months ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- Linux capable RISC-V SoC designed to be readable and useful.☆142Updated 6 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆60Updated 4 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆70Updated 9 months ago
- OpenGL 1.x implementation for FPGAs☆82Updated this week
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆66Updated last week
- Reusable Verilog 2005 components for FPGA designs☆41Updated last month
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆29Updated 2 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆96Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- A pipelined RISC-V processor☆55Updated last year
- SoftCPU/SoC engine-V☆54Updated 3 weeks ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 9 months ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 6 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- Experimental flows using nextpnr for Xilinx devices☆42Updated 3 weeks ago