cloudxcc / ArduissimoLinks
Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
☆21Updated 5 years ago
Alternatives and similar repositories for Arduissimo
Users that are interested in Arduissimo are comparing it to the libraries listed below
Sorting:
- ☆20Updated 3 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- mantle library☆44Updated 2 years ago
- ☆41Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- Top level for the November shuttle☆12Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆32Updated 4 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- ☆33Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- Misc open FPGA flow examples☆8Updated 5 years ago
- Generic Logic Interfacing Project☆46Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆18Updated last month
- Virtual Development Board☆60Updated 3 years ago