cloudxcc / ArduissimoLinks
Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
☆22Updated 6 years ago
Alternatives and similar repositories for Arduissimo
Users that are interested in Arduissimo are comparing it to the libraries listed below
Sorting:
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- ☆20Updated 3 years ago
- Example of how to use UVM with Verilator☆30Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- Top level for the November shuttle☆12Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 2 weeks ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆30Updated last week
- mantle library☆44Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- ☆43Updated 5 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- sample VCD files☆40Updated last week
- Cross compile FPGA tools☆21Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆34Updated 10 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated last week
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 5 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆45Updated 2 years ago