cloudxcc / ArduissimoLinks
Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
☆22Updated 6 years ago
Alternatives and similar repositories for Arduissimo
Users that are interested in Arduissimo are comparing it to the libraries listed below
Sorting:
- ☆20Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Atom Hardware IDE☆13Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 3 weeks ago
- mantle library☆44Updated 3 years ago
- Example of how to use UVM with Verilator☆30Updated last month
- Top level for the November shuttle☆12Updated 4 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆34Updated 10 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 9 months ago
- OpenFPGA☆34Updated 7 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- ☆33Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated last week
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- Yosys Plugins☆22Updated 6 years ago