Alternatives and similar repositories for rapidvpi

Users that are interested in rapidvpi are comparing it to the libraries listed below

• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆43Updated 3 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆47Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated this week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆83Updated 6 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆107Updated this week
• efabless / caravel_user_project_analog
  ☆48Updated 4 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆94Updated 2 weeks ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆64Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 8 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆60Updated last year
• SkyworksSolutionsInc / fplib
  Fixed point math library for SystemVerilog
  ☆25Updated 7 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆130Updated this week
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 9 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆30Updated 5 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆36Updated this week
• mineda-support / ICPS2023_5
  ☆53Updated 4 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆49Updated 2 months ago
• pulp-platform / svase
  ☆32Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆64Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago