ArcSpecter / rapidvpi
Blazingly fast, modern C++ API using coroutines for efficient RTL verification and co-simulation via the VPI interface
☆10Updated 2 months ago
Alternatives and similar repositories for rapidvpi:
Users that are interested in rapidvpi are comparing it to the libraries listed below
- The specification for the FIRRTL language☆51Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 3 months ago
- SystemVerilog frontend for Yosys☆76Updated this week
- ☆16Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- A SystemVerilog source file pickler.☆55Updated 4 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- Raptor end-to-end FPGA Compiler and GUI☆73Updated 2 months ago
- A tool for synthesizing Verilog programs☆72Updated this week
- FPGA tool performance profiling☆102Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- ☆31Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆43Updated 5 months ago
- A Rocket-based RISC-V superscalar in-order core☆30Updated 3 weeks ago
- A pipelined RISC-V processor☆50Updated last year
- Library of open source Process Design Kits (PDKs)☆33Updated last week
- ☆54Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆51Updated last year
- Structural Netlist API (and more) for EDA post synthesis flow development☆92Updated last week
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 3 months ago
- Open-Source Posit RISC-V Core with Quire Capability☆54Updated last month
- ☆31Updated last month
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆80Updated 4 months ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆12Updated 5 months ago
- ☆22Updated last year
- WAL enables programmable waveform analysis.☆146Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated 2 months ago