Alternatives and similar repositories for riscv-llvm-templates

Users that are interested in riscv-llvm-templates are comparing it to the libraries listed below

• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last week
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆40Updated this week
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 weeks ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 2 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated 2 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆36Updated last week
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆36Updated 2 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 3 weeks ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• riscv / riscv-bfloat16
  ☆35Updated 10 months ago
• IntelLabs / t2sp
  Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
  ☆31Updated last year
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆32Updated this week
• riscv / riscv-test-env
  ☆46Updated last week
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• embecosm / embecosm-toolchain-releases
  ☆16Updated 3 weeks ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆11Updated 3 months ago