Alternatives and similar repositories for riscv-llvm-templates

Users that are interested in riscv-llvm-templates are comparing it to the libraries listed below

• rdaly525 / coreir
  ☆103Updated 3 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• riscv / riscv-bfloat16
  ☆37Updated last year
• tenstorrent / rv-core-dv-kit
  ☆25Updated 5 months ago
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆14Updated 2 weeks ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆47Updated last week
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated last month
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆40Updated last month
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆114Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆108Updated 3 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 3 months ago
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated 2 weeks ago
• riscv / riscv-test-env
  ☆50Updated 3 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last month
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 4 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆41Updated 9 months ago