Lichtso / riscv-llvm-templates
Code templates to get started experimenting with the RISC-V LLVM toolchain
☆13Updated 6 years ago
Alternatives and similar repositories for riscv-llvm-templates:
Users that are interested in riscv-llvm-templates are comparing it to the libraries listed below
- ☆33Updated 8 months ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆45Updated 2 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆79Updated 3 months ago
- A Rocket-based RISC-V superscalar in-order core☆30Updated this week
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 8 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆139Updated 3 weeks ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year
- ☆16Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- ☆24Updated last week
- Useful utilities for BAR projects☆31Updated last year
- ☆61Updated 4 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆28Updated last year
- ☆82Updated last month
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆94Updated 3 years ago
- ☆72Updated 4 months ago
- RISC-V architecture concurrency model litmus tests☆74Updated last year
- ☆47Updated this week
- RISC-V Frontend Server☆62Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆99Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago