Alternatives and similar repositories for riscv-llvm-templates:

Users that are interested in riscv-llvm-templates are comparing it to the libraries listed below

• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated last month
• riscv / riscv-bfloat16
  ☆33Updated 8 months ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 4 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 3 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• riscv / riscv-test-env
  ☆45Updated last week
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆40Updated 2 weeks ago
• embecosm / embecosm-toolchain-releases
  ☆16Updated 3 weeks ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆151Updated last year
• rdaly525 / coreir
  ☆102Updated 2 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆75Updated last year
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆96Updated 4 months ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• ucb-bar / testchipip
  ☆82Updated last week
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆41Updated 11 months ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆124Updated 4 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• ucb-bar / ccbench
  Memory System Microbenchmarks
  ☆62Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated this week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago