Toy nmigen RISC V rv32i implementation
☆23Oct 24, 2023Updated 2 years ago
Alternatives and similar repositories for riscy-boi
Users that are interested in riscy-boi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆18Aug 30, 2026Updated last week
- AD9363 + XC6SLX9 board☆12Apr 23, 2019Updated 7 years ago
- Development board for Lattice Crosslink-NX 72QFN☆32Oct 22, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated 2 years ago
- ☆45Mar 12, 2025Updated last year
- OpenGL and GLFW module for ChezScheme☆16Mar 4, 2018Updated 8 years ago
- User-centered experiments with the Sipeed Tang Nano FPGA Board.☆14Jun 29, 2021Updated 5 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆117Jul 20, 2024Updated 2 years ago
- ☆16May 3, 2025Updated last year
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- USB testing framework☆14May 22, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Smol 2-stage RISC-V processor in nMigen☆27May 6, 2021Updated 5 years ago
- assorted library of utility cores for amaranth HDL☆105Sep 17, 2024Updated last year
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 10 years ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆24Aug 30, 2026Updated last week
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Identify and extract files from container formats using unblob.☆29Jul 15, 2026Updated last month
- ☆22Mar 5, 2022Updated 4 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 14 years ago
- FPGA Development for the parallella☆19Aug 9, 2017Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 8 years ago
- General Purpose I/O agent written in UVM☆17Jun 29, 2017Updated 9 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39May 24, 2026Updated 3 months ago
- A safe immutable string format for C☆14Jul 13, 2026Updated last month
- UVM/systemverilog/verilog/python VIM IDE☆17Aug 21, 2013Updated 13 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Aug 27, 2026Updated last week
- vscode support for chez shame☆10Dec 3, 2019Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A configurable USB 2.0 device core