vegaluisjose / reticle-evaluationLinks
Reticle evaluation (PLDI 2021)
☆12Updated 4 years ago
Alternatives and similar repositories for reticle-evaluation
Users that are interested in reticle-evaluation are comparing it to the libraries listed below
Sorting:
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 6 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- ☆40Updated 4 years ago
- A generic test bench written in Bluespec☆55Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- FPGA synthesis tool powered by program synthesis☆52Updated 2 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Manythread RISC-V overlay for FPGA clusters☆38Updated last week
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last week
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- Verilog development and verification project for HOL4☆27Updated 4 months ago
- chipy hdl☆17Updated 7 years ago
- Mutation Cover with Yosys (MCY)☆87Updated 2 weeks ago
- Testing processors with Random Instruction Generation☆46Updated 3 weeks ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆34Updated last week
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- Verilog AST☆21Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Logic circuit analysis and optimization☆42Updated last month
- A core language for rule-based hardware design 🦑☆160Updated 3 months ago
- Haskell library for hardware description☆104Updated last month
- ☆26Updated 2 years ago
- Main page☆128Updated 5 years ago