Alternatives and similar repositories for reticle-evaluation

Users that are interested in reticle-evaluation are comparing it to the libraries listed below

• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated 2 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆53Updated last week
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 9 years ago
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 8 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• David-Durst / embeddedHaskellAetherling
  ☆30Updated 3 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• thoughtpolice / yosys-bluespec
  Yosys plugin for synthesis of Bluespec code
  ☆15Updated 4 years ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆56Updated 5 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆147Updated last month
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆166Updated 2 weeks ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 7 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆17Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 4 months ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year