vegaluisjose / reticle-evaluation
Reticle evaluation (PLDI 2021)
☆12Updated 4 years ago
Alternatives and similar repositories for reticle-evaluation:
Users that are interested in reticle-evaluation are comparing it to the libraries listed below
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Haskell library for hardware description☆103Updated 5 months ago
- FPGA synthesis tool powered by program synthesis☆43Updated this week
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- Galois RISC-V ISA Formal Tools☆58Updated last month
- ☆40Updated 3 years ago
- Verilog development and verification project for HOL4☆26Updated 2 weeks ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- BTOR2 MLIR project☆25Updated last year
- ☆21Updated 9 years ago
- A RiscV processor implementing the RV32I instruction set written in Clash☆53Updated 7 years ago
- Formal specification of RISC-V Instruction Set☆100Updated 4 years ago
- ☆25Updated 2 years ago
- Kansas Lava☆47Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- Generate interface between Clash and Verilator☆22Updated last year
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 7 years ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- RISCV Core written in Calyx☆16Updated 8 months ago
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- ☆29Updated 4 years ago
- chipy hdl☆17Updated 7 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Verilog AST☆21Updated last year
- Projects to get started with Clash☆28Updated 4 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- A core language for rule-based hardware design 🦑☆151Updated 6 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year